MC9S12Q FREESCALE [Freescale Semiconductor, Inc], MC9S12Q Datasheet - Page 530
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MC9S12Q
Manufacturer Part Number
MC9S12Q
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC9S12Q.pdf
(644 pages)
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Chapter 18 64 Kbyte Flash Module (S12FTS64KV4)
18.4.4
On each reset, the Flash module executes a reset sequence to hold CPU activity while loading the following
registers from the Flash array memory according to
18.4.4.1
If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/array being erased is not guaranteed.
18.4.5
The Flash module can generate an interrupt when all Flash commands have completed execution or the
Flash address, data, and command buffers are empty.
18.4.5.1
Figure 18-26
The Flash module uses the CBEIF and CCIF flags in combination with the enable bits CBIE and CCIE to
discriminate for the generation of interrupts.
For a detailed description of these register bits, refer to
(FCNFG)”
530
•
•
FPROT — Flash Protection Register (see
FSEC — Flash Security Register (see
Flash Address, Data, and Command
Buffers are empty
All Flash commands have completed
execution
and
Flash Reset Sequence
Interrupts
Reset While Flash Command Active
Description of Interrupt Operation
shows the logic used for generating interrupts.
Vector addresses and their relative interrupt priority are determined at the
MCU level.
Section 18.3.2.6, “Flash Status Register
Interrupt Source
CBEIE
CBEIF
CCIE
CCIF
Figure 18-26. Flash Interrupt Implementation
Table 18-17. Flash Interrupt Sources
Section
(FSTAT register)
(FSTAT register)
MC9S12Q128
Interrupt Flag
Rev 1.09
NOTE
Section
CBEIF
CCIF
Table
18.3.2.2)
Section 18.3.2.4, “Flash Configuration Register
FLASH INTERRUPT REQUEST
(FSTAT)”.
18.3.2.5)
18-1:
Local Enable
CBEIE
CCIE
Global (CCR) Mask
Freescale Semiconductor
I Bit
I Bit
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