MC9S12Q FREESCALE [Freescale Semiconductor, Inc], MC9S12Q Datasheet - Page 364
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MC9S12Q
Manufacturer Part Number
MC9S12Q
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC9S12Q.pdf
(644 pages)
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Chapter 12 Pulse-Width Modulator (PWM8B4C) Block Description
Read: anytime
Write: anytime
12.3.2.14 PWM Channel Duty Registers (PWMDTYx)
There is a dedicated duty register for each channel. The value in this register determines the duty of the
associated PWM channel. The duty value is compared to the counter and if it is equal to the counter value
a match occurs and the output changes state.
The duty registers for each channel are double buffered so that if they change while the channel is enabled,
the change will NOT take effect until one of the following occurs:
In this way, the output of the PWM will always be either the old duty waveform or the new duty waveform,
not some variation in between. If the channel is not enabled, then writes to the duty register will go directly
to the latches as well as the buffer.
Reference
364
Module Base + 0x0014
Module Base + 0x0015
Reset
Reset
•
•
•
W
W
R
R
The effective period ends
The counter is written (counter resets to 0x0000)
The channel is disabled
Section 12.4.2.3, “PWM Period and Duty,”
Bit 7
Bit 7
0
0
7
7
Reads of this register return the most recent value written. Reads do not
necessarily return the value of the currently active duty due to the double
buffering scheme.
Figure 12-21. PWM Channel Period Registers (PWMPER2)
Figure 12-22. PWM Channel Period Registers (PWMPER3)
6
0
6
0
6
6
5
0
5
0
5
5
MC9S12Q128
Rev 1.09
NOTE
4
0
4
0
4
4
for more information.
3
0
3
0
3
3
2
0
2
0
2
2
Freescale Semiconductor
1
0
1
0
1
1
Bit 0
Bit 0
0
0
0
0
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