MC9S12Q FREESCALE [Freescale Semiconductor, Inc], MC9S12Q Datasheet - Page 385
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MC9S12Q
Manufacturer Part Number
MC9S12Q
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC9S12Q.pdf
(644 pages)
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13.3.2.3
Read: Anytime
Write: Anytime
Freescale Semiconductor
Module Base + 0x_0003
Reset
Field
TCIE
ILIE
TIE
RIE
RE
TE
7
6
5
4
3
2
W
R
Transmitter Interrupt Enable Bit — TIE enables the transmit data register empty flag, TDRE, to generate
interrupt requests.
0 TDRE interrupt requests disabled
1 TDRE interrupt requests enabled
Transmission Complete Interrupt Enable Bit — TCIE enables the transmission complete flag, TC, to generate
interrupt requests.
0 TC interrupt requests disabled
1 TC interrupt requests enabled
Receiver Full Interrupt Enable Bit — RIE enables the receive data register full flag, RDRF, or the overrun flag,
OR, to generate interrupt requests.
0 RDRF and OR interrupt requests disabled
1 RDRF and OR interrupt requests enabled
Idle Line Interrupt Enable Bit — ILIE enables the idle line flag, IDLE, to generate interrupt requests.
0 IDLE interrupt requests disabled
1 IDLE interrupt requests enabled
Transmitter Enable Bit — TE enables the SCI transmitter and configures the TXD pin as being controlled by
the SCI. The TE bit can be used to queue an idle preamble.
0 Transmitter disabled
1 Transmitter enabled
Receiver Enable Bit — RE enables the SCI receiver.
0 Receiver disabled
1 Receiver enabled
TIE
SCI Control Register 2 (SCICR2)
0
7
LOOPS
0
1
1
TCIE
RSRC
0
6
0
1
x
Figure 13-5. SCI Control Register 2 (SCICR2)
Normal operation
Loop mode with Rx input internally connected to Tx output
Single-wire mode with Rx input connected to TXD
Table 13-4. SCICR2 Field Descriptions
RIE
0
5
Table 13-3. Loop Functions
Chapter 13 Serial Communications Interface (S12SCIV2) Block Description
MC9S12Q128
Rev 1.09
ILIE
0
4
Description
Function
TE
0
3
RE
0
2
RWU
0
1
SBK
0
0
385
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