MC9S12Q FREESCALE [Freescale Semiconductor, Inc], MC9S12Q Datasheet - Page 301
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MC9S12Q
Manufacturer Part Number
MC9S12Q
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC9S12Q.pdf
(644 pages)
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10.3.2.6
This register contains the interrupt enable bits for the interrupt flags described in the CANRFLG register.
Read: Anytime
Write: Anytime when not in initialization mode
Freescale Semiconductor
Module Base + 0x0005
RSTATE[1:0]
TSTATE[1:0]
WUPIE
CSCIE
Field
5:4
3:2
7
6
Reset:
(1)
W
R
Wake-Up Interrupt Enable
0 No interrupt request is generated from this event.
1 A wake-up event causes a Wake-Up interrupt request.
CAN Status Change Interrupt Enable
0 No interrupt request is generated from this event.
1 A CAN Status Change event causes an error interrupt request.
Receiver Status Change Enable — These RSTAT enable bits control the sensitivity level in which receiver state
changes are causing CSCIF interrupts. Independent of the chosen sensitivity level the RSTAT flags continue to
indicate the actual receiver state and are only updated if no CSCIF interrupt is pending.
00 Do not generate any CSCIF interrupt caused by receiver state changes.
01 Generate CSCIF interrupt only if the receiver enters or leaves “bus-off” state. Discard other receiver state
10 Generate CSCIF interrupt only if the receiver enters or leaves “RxErr” or “bus-off”
11 Generate CSCIF interrupt on all state changes.
Transmitter Status Change Enable — These TSTAT enable bits control the sensitivity level in which transmitter
state changes are causing CSCIF interrupts. Independent of the chosen sensitivity level, the TSTAT flags
continue to indicate the actual transmitter state and are only updated if no CSCIF interrupt is pending.
00 Do not generate any CSCIF interrupt caused by transmitter state changes.
01 Generate CSCIF interrupt only if the transmitter enters or leaves “bus-off” state. Discard other transmitter
10 Generate CSCIF interrupt only if the transmitter enters or leaves “TxErr” or “bus-off” state. Discard other
11 Generate CSCIF interrupt on all state changes.
MSCAN Receiver Interrupt Enable Register (CANRIER)
WUPIE
The CANRIER register is held in the reset state when the initialization mode
is active (INITRQ=1 and INITAK=1). This register is writable when not in
initialization mode (INITRQ=0 and INITAK=0).
The RSTATE[1:0], TSTATE[1:0] bits are not affected by initialization
mode.
changes for generating CSCIF interrupt.
receiver state changes for generating CSCIF interrupt.
state changes for generating CSCIF interrupt.
transmitter state changes for generating CSCIF interrupt.
0
7
Figure 10-9. MSCAN Receiver Interrupt Enable Register (CANRIER)
CSCIE
Table 10-10. CANRIER Register Field Descriptions
6
0
RSTATE1
0
5
MC9S12Q128
Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2)
RSTATE0
Rev 1.09
NOTE
4
0
Description
TSTATE1
0
3
TSTATE0
2
0
(2)
OVRIE
state. Discard other
0
1
RXFIE
0
0
301
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