MC9S12Q FREESCALE [Freescale Semiconductor, Inc], MC9S12Q Datasheet - Page 320
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MC9S12Q
Manufacturer Part Number
MC9S12Q
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC9S12Q.pdf
(644 pages)
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Module Base + 0x0004 (DSR0)
Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV2)
10.3.3.2
The eight data segment registers, each with bits DB[7:0], contain the data to be transmitted or received.
The number of bytes to be transmitted or received is determined by the data length code in the
corresponding DLR register.
320
Module Base + 0x00X3
DB[7:0]
Field
7:0
Reset:
Reset:
W
W
Figure 10-33. Data Segment Registers (DSR0–DSR7) — Extended Identifier Mapping
R
R
0x0005 (DSR1)
0x0006 (DSR2)
0x0007 (DSR3)
0x0008 (DSR4)
0x0009 (DSR5)
0x000A (DSR6)
0x000B (DSR7)
Data bits 7:0
Data Segment Registers (DSR0-7)
DB7
7
x
7
x
Figure 10-32. Identifier Register 3 — Standard Mapping
= Unused; always read ‘x’
Table 10-30. DSR0–DSR7 Register Field Descriptions
DB6
6
x
6
x
DB5
5
x
5
x
MC9S12Q128
Rev 1.09
DB4
4
x
4
x
Description
DB3
x
x
3
3
DB2
2
x
2
x
Freescale Semiconductor
DB1
x
x
1
1
DB0
0
x
0
x
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