MC9S12Q FREESCALE [Freescale Semiconductor, Inc], MC9S12Q Datasheet - Page 49

• Manufacturer Part Number: MC9S12Q
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

1. The Port E output buffer enable signal control at reset is determined by the PEAR register and is mode dependent. For
1.3.3
Not Bonded Pins:
Freescale Semiconductor
Function 1
Pin Name
example, in special test mode RDWE = LSTRE = 1 which enables the PE[3:2] output buffers and disables the pull-ups. Refer
to S12_MEBI user guide for PEAR register details.
PP[2:0]
PS[3:2]
PJ[7:6]
PT[7:5]
PT[4:0]
PM5
PM4
PM3
PM2
PM1
PM0
PS1
PS0
If the port pins are not bonded out in the chosen package the user should initialize the registers to
be inputs with enabled pull resistance to avoid excess current consumption. This applies to the
following pins:
(48LQFP): Port A[7:1], Port B[7:5], Port B[3:0], PortE[6,5,3,2], Port P[7:6], PortP[4:0], Port
J[7:6], PortS[3:2]
(52LQFP): Port A[7:3], Port B[7:5], Port B[3:0], PortE[6,5,3,2], Port P[7:6], PortP[2:0], Port
J[7:6], PortS[3:2]
Pin Initialization for 48- and 52-Pin LQFP Bond Out Versions
Function 2
Pin Name
KWP[2:0]
KWJ[7:6]
IOC[7:5]
IOC[4:2]
RXCAN
TXCAN
MOSI
MISO
SCK
RXD
TXD
SS
—
Function 3
Pin Name
PW[2:0]
PW[3:0]
—
—
—
—
—
—
—
—
—
—
—
Table 1-5. Signal Properties (continued)
Domain
Power
V
V
V
V
V
V
V
V
V
V
V
V
V
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
DDX
PERM/
PERM/
PERM/
PERM/
PERM/
PERM/
MC9S12Q128
PERP/
PERS/
PERS/
PERS/
PERT/
PERT/
PERJ/
PPSM
PPSM
PPSM
PPSM
PPSM
PPSM
CTRL
PPSP
PPSS
PPSS
PPSS
PPST
PPST
PPSJ
Rev 1.09
Internal Pull
Resistor
Disabled
Disabled
Disabled
Disabled
Reset
State
Chapter 1 MC9S12Q Device Overview (MC9S12Q128-Family)
Up
Up
Up
Up
Up
Up
Up
Up
Up
Port P I/O pins, keypad wake-up, PWM outputs
Port J I/O pins and keypad wake-up
Port M I/O pin and SPI SCK signal
Port M I/O pin and SPI MOSI signal
Port M I/O pin and SPI SS signal
Port M I/O pin and SPI MISO signal
Port M I/O pin and CAN transmit signal
Port M I/O pin and CAN receive signal
Port S I/O pins
Port S I/O pin and SCI transmit signal
Port S I/O pin and SCI receive signal
Port T I/O pins shared with timer (TIM)
Port T I/O pins shared with timer and PWM
Description
49