MC9S12Q FREESCALE [Freescale Semiconductor, Inc], MC9S12Q Datasheet - Page 627
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MC9S12Q
Manufacturer Part Number
MC9S12Q
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC9S12Q.pdf
(644 pages)
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In
A.6.2
In
Freescale Semiconductor
Num
10
11
12
13
Table A-21
Figure A-8
1
1
2
3
4
5
6
9
(CPOL 1)
(CPOL 0)
(OUTPUT)
NOTE: Not defined!
(INPUT)
(INPUT)
(INPUT)
(INPUT)
MOSI
MISO
SCK
SCK
C
D
D
D
D
D
D
D
D
D
D
P
P
SS
Slave Mode
10
7
the timing diagram for slave mode with transmission format CPHA=0 is depicted.
the timing characteristics for master mode are listed.
SCK Frequency
SCK Period
Enable Lead Time
Enable Lag Time
Clock (SCK) High or Low Time
Data Setup Time (Inputs)
Data Hold Time (Inputs)
Data Valid after SCK Edge
Data Valid after SS fall (CPHA=0)
Data Hold Time (Outputs)
Rise and Fall Time Inputs
Rise and Fall Time Outputs
note
see
2
5
Characteristic
MSB IN
Table A-21. SPI Master Mode Timing Characteristics
SLAVE MSB
6
4
Figure A-8. SPI Slave Timing (CPHA=0)
1
4
BIT 6 . . . 1
BIT 6 . . . 1
9
MC9S12Q128
Rev 1.09
12
12
Symbol
t
t
t
f
t
wsck
t
lead
t
vsck
t
t
t
sck
sck
t
vss
t
lag
su
ho
rfo
hi
rfi
11
1/2048
SLAVE LSB OUT
Min
LSB IN
20
—
—
—
—
—
—
—
2
8
8
13
13
11
3
Appendix A Electrical Characteristics
Typ
1/2
1/2
1/2
—
—
—
—
—
—
—
—
—
NOTE
SEE
2048
Max
1 2
30
15
—
—
—
—
—
—
8
8
8
Unit
f
t
t
t
t
bus
bus
ns
ns
ns
ns
ns
ns
ns
sck
sck
sck
627
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