MC9S12Q FREESCALE [Freescale Semiconductor, Inc], MC9S12Q Datasheet - Page 537
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MC9S12Q
Manufacturer Part Number
MC9S12Q
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC9S12Q.pdf
(644 pages)
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19.3.2.1
The FCLKDIV register is used to control timed events in program and erase algorithms.
All bits in the FCLKDIV register are readable, bits 6–0 are write once and bit 7 is not writable.
19.3.2.2
The FSEC register holds all bits associated with the security of the MCU and Flash module.
All bits in the FSEC register are readable but not writable.
The FSEC register is loaded from the Flash configuration field at 0xFF0F during the reset sequence,
indicated by F in
Freescale Semiconductor
Module Base + 0x0000
Module Base + 0x0001
FDIV[5:0]
FDIVLD
PRDIV8
Reset
Reset
Field
5–0
7
6
W
W
R
R
KEYEN1
FDIVLD
Clock Divider Loaded
0 FCLKDIV register has not been written
1 FCLKDIV register has been written to since the last reset
Enable Prescalar by 8
0 The oscillator clock is directly fed into the Flash clock divider
1 The oscillator clock is divided by 8 before feeding into the Flash clock divider
Clock Divider Bits — The combination of PRDIV8 and FDIV[5:0] must divide the oscillator clock down to a
frequency of 150 kHz – 200 kHz. The maximum divide ratio is 512. Refer to
FCLKDIV Register”
Flash Clock Divider Register (FCLKDIV)
Flash Security Register (FSEC)
F
0
7
7
Figure
= Unimplemented or Reserved
= Unimplemented or Reserved
KEYEN0
PRDIV8
19-5.
0
F
6
6
Figure 19-4. Flash Clock Divider Register (FCLKDIV)
for more information.
Figure 19-5. Flash Security Register (FSEC)
Table 19-3. FCLKDIV Field Descriptions
FDIV5
NV5
0
F
5
5
MC9S12Q128
FDIV4
NV4
Rev 1.09
0
F
4
4
Description
FDIV3
NV3
F
0
3
3
Chapter 19 96 Kbyte Flash Module (S12FTS96KV1)
FDIV2
NV2
0
F
2
2
Section 19.4.1.1, “Writing the
FDIV1
SEC1
0
F
1
1
FDIV0
SEC0
F
0
0
0
537
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