HD6432621 Hitachi, HD6432621 Datasheet - Page 1012

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

SSR1—Serial Status Register 1
968
Bit
Initial value
Read/Write
Notes:
For details, see section 14.2.2, Serial Status Register (SSR).
* Can only be written with 0 for flag clearing.
:
:
:
R/(W)*
TDRE
Transmit data register empty
7
1
0 [Clearing conditions]
1
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and writes data to TDR
[Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written to TDR
Receive data register full
0 [Clearing conditions]
1
R/(W)*
RDRF
• When 0 is written to RDRF after reading RDRF = 1
• When the DTC is activated by an RXI interrupt and reads data from RDR
[Setting condition]
When serial reception ends normally and receive data is transferred from RSR to RDR
6
0
Overrun error
0 [Clearing condition]
1
When 0 is written to ORER after reading ORER = 1
[Setting condition]
When the next serial reception is completed while RDRF = 1
R/(W)*
ORER
5
0
Error signal status
Note:
0 [Clearing conditions]
1
• Upon reset, and in standby mode or module stop mode
• When 0 is written to ERS after reading ERS = 1
[Setting condition]
When the low level of the error signal is sampled
Parity error
Clearing the TE bit in SCR to 0 does not affect the ERS flag,
which retains its previous state.
R/(W)*
0 [Clearing condition]
1
ERS
Note: etu: Elementary Time Unit (time for transfer of 1 bit)
Transmit end
0 [Clearing conditions]
1
When 0 is written to PER after reading PER = 1
[Setting condition]
When, in reception, the number of 1 bits in the receive data plus the
parity bit does not match the parity setting (even or odd) specified by
the O/E bit in SMR
4
0
• When 0 is written to TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and writes data to TDR
[Setting conditions]
• Upon reset, and in standby mode or module stop mode
• When the TE bit in SCR is 0 and the ERS bit is also 0
• When TDRE = 1 ERS = 0 (normal transmission) 2.5 etu after
• When TDRE = 1 ERS = 0 (normal transmission) 1.5 etu after
• When TDRE = 1 ERS = 0 (normal transmission) 1.0 etu after
• When TDRE = 1 ERS = 0 (normal transmission) 1.0 etu after
transmission of a 1-byte serial character when GM = 0 and BLK = 0
transmission of a 1-byte serial character when GM = 0 and BLK = 1
transmission of a 1-byte serial character when GM = 1 and BLK = 0
transmission of a 1-byte serial character when GM = 1 and BLK = 1
H'FF84
R/(W)*
PER
3
0
Multiprocessor bit
0 [Clearing condition]
1
When data with a 0 multiprocessor bit is received
[Setting condition]
When data with a 1 multiprocessor bit is received
TEND
R
2
1
Smart Card Interface
Multiprocessor bit transfer
0 Data with a 0 multiprocessor
1
bit is transmitted
Data with a 1 multiprocessor
bit is transmitted
MPB
R
1
0
MPBT
R/W
0
0