HD6432621 Hitachi, HD6432621 Datasheet - Page 587

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Bit 4—Bus Operation Interrupt Mask (IMR12): Enables or disables interrupt requests due to
bus operation in sleep mode.
Bit 4: IMR12
0
1
Bit 1—Unread Interrupt Mask (IMR9): Enables or disables unread receive message overwrite
interrupt requests.
Bit 1: IMR9
0
1
Bit 0—Mailbox Empty Interrupt Mask (IMR8): Enables or disables mailbox empty interrupt
requests.
Bit 0: IMR8
0
1
15.2.14 Receive Error Counter (REC)
The receive error counter (REC) is an 8-bit read-only register that functions as a counter indicating
the number of receive message errors on the CAN bus. The count value is stipulated in the CAN
protocol.
Initial value:
REC
R/W:
Bit:
Description
Bus operation interrupt request (OVR0) to CPU by IRR12 enabled
Bus operation interrupt request (OVR0) to CPU by IRR12 disabled
Description
Unread message overwrite interrupt request (OVR0) to CPU by IRR9
enabled
Unread message overwrite interrupt request (OVR0) to CPU by IRR9
disabled
Description
Mailbox empty interrupt request (SLE0) to CPU by IRR8 enabled
Mailbox empty interrupt request (SLE0) to CPU by IRR8 disabled
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
(Initial value)
(Initial value)
(Initial value)
0
0
R
543