HD6432621 Hitachi, HD6432621 Datasheet - Page 36

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

11.3 Operation ........................................................................................................................... 385
11.4 Usage Notes ....................................................................................................................... 394
Section 12 Watchdog Timer
12.1 Overview............................................................................................................................ 397
12.2 Register Descriptions......................................................................................................... 401
12.3 Operation ........................................................................................................................... 410
12.4 Interrupts............................................................................................................................ 414
12.5 Usage Notes ....................................................................................................................... 414
Section 13 Serial Communication Interface (SCI)
13.1 Overview ........................................................................................................................... 417
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11.2.3 Next Data Registers H and L (NDRH, NDRL).................................................... 377
11.2.4 Notes on NDR Access.......................................................................................... 377
11.2.5 PPG Output Control Register (PCR).................................................................... 379
11.2.6 PPG Output Mode Register (PMR)...................................................................... 381
11.2.7 Port 1 Data Direction Register (P1DDR) ............................................................. 384
11.2.8 Module Stop Control Register A (MSTPCRA).................................................... 384
11.3.1 Overview .............................................................................................................. 385
11.3.2 Output Timing ...................................................................................................... 386
11.3.3 Normal Pulse Output............................................................................................ 387
11.3.4 Non-Overlapping Pulse Output ............................................................................ 389
11.3.5 Inverted Pulse Output ........................................................................................... 392
11.3.6 Pulse Output Triggered by Input Capture ............................................................ 393
12.1.1 Features ................................................................................................................ 397
12.1.2 Block Diagram...................................................................................................... 398
12.1.3 Pin Configuration ................................................................................................. 400
12.1.4 Register Configuration ......................................................................................... 400
12.2.1 Timer Counter (TCNT) ........................................................................................ 401
12.2.2 Timer Control/Status Register (TCSR) ................................................................ 401
12.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 406
12.2.4 Pin Function Control Register (PFCR) ................................................................ 407
12.2.5 Notes on Register Access ..................................................................................... 408
12.3.1 Watchdog Timer Operation.................................................................................. 410
12.3.2 Interval Timer Operation...................................................................................... 412
12.3.3 Timing of Setting Overflow Flag (OVF).............................................................. 412
12.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) ......................... 413
12.5.1 Contention between Timer Counter (TCNT) Write and Increment ..................... 414
12.5.2 Changing Value of PSS and CKS2 to CKS0........................................................ 415
12.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 415
12.5.4 System Reset by WDTOVF Signal...................................................................... 415
12.5.5 Internal Reset in Watchdog Timer Mode ............................................................. 415
12.5.6 OVF Flag Clearing in Interval Timer Mode ........................................................ 416
............................................................................................. 397
.................................................... 417