HD6432621 Hitachi, HD6432621 Datasheet - Page 604

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Table 15-4 Setting Range for TSEG1 and TSEG2 in BCR
Notes: The time quanta value for TSEG1 and TSEG2 is the TSEG value + 1.
Mailbox Transmit/Receive Settings: HCAN0, 1 each have 16 mailboxes. Mailbox 0 is receive-
only, while mailboxes 1 to 15 can be set for transmission or reception. Mailboxes that can be set
for transmission or reception must be designated either for transmission use or for reception use
before communication begins. The Initial status of mailboxes 1 to 15 is for transmission (while
mailbox 0 is for reception only). Mailbox transmit/receive settings are not initialized by a software
reset.
560
(BCR [11:8])
Setting for transmission
Transmit mailbox setting (mailboxes 1 to 15)
Clearing a bit to 0 in the mailbox configuration register (MBCR) designates the corresponding
mailbox for transmission use. After a reset, mailboxes are initialized for transmission use, so
this setting is not necessary.
Setting for reception
Transmit/receive mailbox setting (mailboxes 1 to 15)
Setting a bit to 1 in the mailbox configuration register (MBCR) designates the corresponding
mailbox for reception use. When setting mailboxes for reception, to improve message
transmission efficiency, high-priority messages should be set in low-to-high mailbox order
(priority order: mailbox 1 (MCx[1]) > mailbox 15 (MCx[15]).
TSEG1
*
Setting is enabled except when BRP [13:8] = B'000000.
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Yes*
Yes*
Yes*
Yes*
Yes*
Yes*
Yes*
Yes*
Yes*
Yes*
Yes*
Yes*
001
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
010
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
011
No
TSEG2 (BCR [14:12])
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
100
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
101
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
110
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
111
No
No
No
No
No