HD6432621 Hitachi, HD6432621 Datasheet - Page 755

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Bits 2 to 0—System clock select (SCK2 to SCK0): These bits select the bus master clock in
high-speed mode, medium-speed mode, and sub-active mode.
Set SCK2 to SCK0 all to 0 when shifting to operation in watch mode or sub-active mode.
Bit 2
SCK2
0
1
21B.2.3 Low-Power Control Register (LPWRCR)
The LPWRCR is an 8-bit read/write register that controls the low power dissipation modes.
The LPWRCR is initialized to H'00 at a reset and when in hardware standby mode. It is not
initialized in software standby mode. The following describes bits 7 to 2. For details of other bits,
see section 20.2.2, Low-Power Control Register (LPWRCR).
Bit 7—Direct Transition ON Flag (DTON): When shifting to low power dissipation mode by
executing the SLEEP instruction, this bit specifies whether or not to make a direct transition
between high-speed mode or medium-speed mode and the sub-active modes. The selected
operating mode after executing the SLEEP instruction is determined by the combination of other
control bits.
Bit
Initial value :
R/W
Bit 1
SCK1
0
1
0
1
:
:
DTON
R/W
Bit 0
SCK0
0
1
0
1
0
1
—
7
0
LSON
R/W
Description
Bus master in high-speed mode
Medium-speed clock is ø/2
Medium-speed clock is ø/4
Medium-speed clock is ø/8
Medium-speed clock is ø/16
Medium-speed clock is ø/32
—
6
0
NESEL
R/W
5
0
SUBSTP RFCUT
R/W
4
0
R/W
3
0
R/W
—
2
0
STC1
R/W
1
0
(Initial value)
STC0
R/W
0
0
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