HD6432621 Hitachi, HD6432621 Datasheet - Page 684
HD6432621
Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
1.HD6432621.pdf
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19.7.1
Program Mode
When writing data or programs to flash memory, the program/program-verify flowchart shown in
figure 19-11 should be followed. Performing programming operations according to this flowchart
will enable data or programs to be written to flash memory without subjecting the device to
voltage stress or sacrificing program data reliability. Programming should be carried out 128 bytes
at a time.
The wait times after bits are set or cleared in the flash memory control register 1 (FLMCR1) and
the maximum number of programming operations (N) are shown in table 22-9 in section 22.6,
Flash Memory Characteristics.
Following the elapse of ( 0) µs or more after the SWE1 bit is set to 1 in FLMCR1, 128-byte
program data is stored in the program data area and reprogram data area, and the 128-byte data in
the program data area in RAM is written consecutively to the program address (the lower 8 bits of
the first address written to must be H'00 or H'80). 128 consecutive byte data transfers are
performed. The program address and program data are latched in the flash memory. A 128-byte
data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must
be written to the extra addresses.
Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc.
Set 6.6 ms as the WDT overflow period. After this, preparation for program mode (program setup)
is carried out by setting the PSU1 bit in FLMCR1, and after the elapse of (y) µs or more, the
operating mode is switched to program mode by setting the P1 bit in FLMCR1. The time during
which the P1 bit is set is the flash memory programming time. Refer to the table in figure 19-11
for the programming time.
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