HD6432621 Hitachi, HD6432621 Datasheet - Page 620

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

15.3.6
The HCAN halt mode is provided to enable mailbox settings to be changed without performing an
HCAN hardware or software reset. Figure 15-12 shows a flowchart of the HCAN halt mode.
HCAN halt mode is entered by setting the halt request bit (MCR1) to 1 in the master control
register (MCR). If the CAN bus is operating, the transition to HCAN halt mode is delayed until
the bus becomes idle.
HCAN halt mode is cleared by clearing MCR1 to 0.
15.3.7
There are 12 HCAN interrupt sources, to which five independent interrupt vectors are assigned.
Table 15-5 lists the HCAN interrupt sources.
With the exception of the reset processing vector (IRR0), these sources can be masked. Masking is
implemented using the mailbox interrupt mask register (MBIMR) and interrupt mask register
(IMR).
576
HCAN Halt Mode
Interrupt Interface
CAN bus communication possible
MBCR setting
MCR1 = 1
MCR1 = 0
Bus idle?
Figure 15-12 HCAN Halt Mode Flowchart
Yes
No
: Settings by user
: Processing by hardware