HD6432621 Hitachi, HD6432621 Datasheet - Page 309
![no-image](/images/manufacturer_photos/0/3/301/hitachi_sml.jpg)
HD6432621
Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
1.HD6432621.pdf
(1069 pages)
- Current page: 309 of 1069
- Download datasheet (5Mb)
Port D Data Register (PDDR)
PDDR is an 8-bit readable/writable register that stores output data for the port D pins (PD7 to
PD0).
PDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode.
Port D Register (PORTD)
Note: * Determined by state of pins PD7 to PD0.
PORTD is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port D pins (PD7 to PD0) must always be performed on PDDR.
If a port D read is performed while PDDDR bits are set to 1, the PDDR values are read. If a port D
read is performed while PDDDR bits are cleared to 0, the pin states are read.
After a reset and in hardware standby mode, PORTD contents are determined by the pin states, as
PDDDR and PDDR are initialized. PORTD retains its prior state in software standby mode.
Bit
Initial value :
R/W
Bit
Initial value :
R/W
:
:
:
:
PD7DR
R/W
PD7
—*
7
0
7
R
PD6DR
R/W
PD6
—*
6
0
6
R
PD5DR
R/W
PD5
—*
5
0
5
R
PD4DR
R/W
PD4
—*
4
0
4
R
PD3DR
R/W
PD3
—*
3
0
3
R
PD2DR
R/W
PD2
—*
2
0
2
R
PD1DR
R/W
PD1
—*
1
0
1
R
PD0DR
R/W
PD0
—*
0
0
0
R
265
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