HD6432621 Hitachi, HD6432621 Datasheet - Page 147
HD6432621
Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
1.HD6432621.pdf
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5.3
Interrupt sources comprise external interrupts (NMI and IRQ5 to IRQ0) and internal interrupts (48
sources: H8S/2626 Series, 47 sources: H8S/2623 Series).
5.3.1
There are seven external interrupts: NMI and IRQ5 to IRQ0. These interrupts can be used to
restore the H8S/2626 Series or H8S/2623 Series chip from software standby mode.
NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU
regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG
bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling
edge on the NMI pin.
The vector number for NMI interrupt exception handling is 7.
IRQ5 to IRQ0 Interrupts: Interrupts IRQ5 to IRQ0 are requested by an input signal at pins IRQ5
to IRQ0. Interrupts IRQ5 to IRQ0 have the following features:
A block diagram of interrupts IRQ5 to IRQ0 is shown in figure 5-2.
Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
edge, rising edge, or both edges, at pins IRQ5 to IRQ0.
Enabling or disabling of interrupt requests IRQ5 to IRQ0 can be selected with IER.
The interrupt priority level can be set with IPR.
The status of interrupt requests IRQ5 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0
by software.
IRQn input
Note: n = 5 to 0
Interrupt Sources
External Interrupts
Figure 5-2 Block Diagram of Interrupts IRQ5 to IRQ0
IRQnSCA, IRQnSCB
detection circuit
Edge/level
Clear signal
R
S
IRQnF
Q
IRQnE
IRQn interrupt
request
103
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