HD6432621 Hitachi, HD6432621 Datasheet - Page 341

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HD6432621

Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
Channel
0
Notes: *1 When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and ø/1 is used as the TCNT1
*2 When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this
Bit 7
IOD3
0
1
count clock, this setting is invalid and input capture is not generated.
setting is invalid and input capture/output compare is not generated.
Bit 6
IOD2
0
1
0
1
Bit 5
IOD1
0
1
0
1
0
1
*
Bit 4
IOD0
0
1
0
1
0
1
0
1
0
1
*
*
Description
TGR0D
is output
compare
register*
TGR0D
is input
capture
register*
2
2
Output disabled
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input
source is
TIOCD0 pin
Capture input
source is channel
1/count clock
0 output at compare match
1 output at compare match
Toggle output at compare
match
0 output at compare match
1 output at compare match
Toggle output at compare
match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT1
count-up/count-down*
(Initial value)
*: Don’t care
1
297

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