HD6432621 Hitachi, HD6432621 Datasheet - Page 173

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

6.3
The operation flow from break condition setting to PC break interrupt exception handling is shown
in sections 6.3.1, PC Break Interrupt Due to Instruction Fetch and 6.3.2, PC Break Interrupt Due to
Data Access, taking the example of channel A.
6.3.1
(1) Initial settings
(2) Satisfaction of break condition
(3) Interrupt handling
6.3.2
(1) Initial settings
Set the break address in BARA. For a PC break caused by an instruction fetch, set the
Set the break conditions in BCRA.
When the instruction at the set address is fetched, a PC break request is generated
After priority determination by the interrupt controller, PC break interrupt exception
Set the break address in BARA. For a PC break caused by a data access, set the target
Set the break conditions in BCRA.
address of the first instruction byte as the break address.
BCRA bit 6 (CDA): With a PC break caused by an instruction fetch, the bus master must
be the CPU. Set 0 to select the CPU.
BCRA bits 5–3 (BAMA2–0): Set the address bits to be masked.
BCRA bits 2–1 (CSELA1–0): Set 00 to specify an instruction fetch as the break condition.
BCRA bit 0 (BIEA): Set to 1 to enable break interrupts.
immediately before execution of the fetched instruction, and the condition match flag
(CMFA) is set.
handling is started.
ROM, RAM, I/O, or external address space address as the break address. Stack operations
and branch address reads are included in data accesses.
BCRA bit 6 (CDA): Select the bus master.
BCRA bits 5–3 (BAMA2–0): Set the address bits to be masked.
BCRA bits 2–1 (CSELA1–0): Set 01, 10, or 11 to specify data access as the break
condition.
BCRA bit 0 (BIEA): Set to 1 to enable break interrupts.
Operation
PC Break Interrupt Due to Instruction Fetch
PC Break Interrupt Due to Data Access
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