HD6432621 Hitachi, HD6432621 Datasheet - Page 582

• Manufacturer Part Number: HD6432621
• Description: (HD64F262x Series) 16-Bit Microcomputer
• Manufacturer: Hitachi

Bit 9—Receive Message Interrupt Flag (IRR1): Status flag indicating that a mailbox (buffer)
receive message has been received normally.
Bit 9: IRR1
0
1
Bit 8—Reset Interrupt Flag (IRR0): Status flag indicating that the HCAN module has been
reset. This bit cannot be masked in the interrupt mask register (IMR). If this bit is not cleared after
reset input or recovery from software standby mode, interrupt handling will be performed as soon
as interrupts are enabled by the interrupt controller.
Bit 8: IRR0
0
1
Note: * After reset or hardware standby release, the module stop bit is initialized to 1, and so the
Bits 7 to 5, 3, and 2—Reserved: These bits always read 0. The write value should always be 0.
Bit 4—Bus Operation Interrupt Flag (IRR12): Status flag indicating detection of a dominant bit
due to bus operation when the HCAN module is in HCAN sleep mode.
Bit 4: IRR12
0
1
538
HCAN enters the module stop state.
Description
[Clearing condition]
Clearing of all bits in RXPR (receive complete register) of mailbox for which
receive interrupt requests are enabled by MBIMR
Data frame or remote frame received and stored in mailbox
[Setting conditions]
When data frame or remote frame reception is completed, when
corresponding MBIMR = 0
Description
[Clearing condition]
Writing 1
Hardware reset (HCAN module stop*, software standby)
[Setting condition]
When reset processing is completed after a hardware reset (HCAN module
stop*, software standby)
Description
CAN bus idle state
[Clearing condition]
Writing 1
CAN bus operation in HCAN sleep mode
[Setting condition]
Bus operation (dominant bit detection) in HCAN sleep mode
(Initial value)
(Initial value)
(Initial value)