HD6432621 Hitachi, HD6432621 Datasheet - Page 470
HD6432621
Manufacturer Part Number
HD6432621
Description
(HD64F262x Series) 16-Bit Microcomputer
Manufacturer
Hitachi
Datasheet
1.HD6432621.pdf
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Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode.
The STOP bits setting is only valid in asynchronous mode. If clocked synchronous mode is set the
STOP bit setting is invalid since stop bits are not added.
Bit 3
STOP
0
1
In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit
character.
Bit 2—Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format
is selected, the PE bit and O/E bit parity settings are invalid. The MP bit setting is only valid in
asynchronous mode; it is invalid in clocked synchronous mode.
For details of the multiprocessor communication function, see section 13.3.3, Multiprocessor
Communication Function.
Bit 2
MP
0
1
426
Description
1 stop bit: In transmission, a single 1 bit (stop bit) is added to the end
2 stop bits: In transmission, two 1 bits (stop bits) are added to the end of a transmit
Description
Multiprocessor function disabled
Multiprocessor format selected
of a transmit character before it is sent.
character before it is sent.
(Initial value)
(Initial value)
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