XC68HC08KH12 Motorola, XC68HC08KH12 Datasheet - Page 103

• Manufacturer Part Number: XC68HC08KH12
• Description: MICROCONTROLLER
• Manufacturer: Motorola

MC68HC(7)08KH12
MOTOROLA
NOTE:
—
Rev. 1.0
PLLON — PLL On Bit
BCS — Base Clock Select Bit
PLLON and BCS have built-in protection that prevents the base clock
selector circuit from selecting the VCO clock as the source of the base
clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS
is set, and BCS cannot be set when PLLON is clear. If the PLL is off
(PLLON = 0), selecting CGMPCLK/CGMVCLK requires two writes to the
PLL control register. (See
PRE1 and PRE0 — Prescaler program bits
This read/write bit activates the PLL and enables the VCO clock,
CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the
base clock, CGMOUT (BCS = 1). (See
Circuit.) Reset sets this bit so that the loop can stabilize as the MCU
is powering up.
This read/write bit selects either the crystal oscillator clock
(CGMXCLK) or the VCO clocks (CGMPCLK and CGMVCLK) to use
as base clocks for the MCU.
BCS cannot be set while the PLLON bit is clear. After toggling BCS,
it may take up to three CGMXCLK and three CGMPCLK cycles to
complete the transition from one source clock to the other. During the
transition, CGMOUT is held in stasis. (See
Selector
These read/write bits control a prescaler that selects the prescaler
power-of-two multiplier P. (See
Programming the
PLLON bit is set. Reset clears these bits.
1 = PLL on
0 = PLL off
1 = Selects the VCO clocks for the base clock.
0 = Selects the crystal oscillator clock for the base clock.
CGMPCLK divided by two drives CGMOUT,
CGMVCLK (48MHz) drives USBCLK
CGMXCLK divided by two drives CGMOUT,
CGMXCLK drives USBCLK
Clock Generator Module (CGM)
Circuit.) Reset clears the BCS bit.
PLL.) PRE1:PRE0 cannot be written when the
8.4.8 Base Clock Selector
8.4.3 PLL Circuits
8.4.8 Base Clock Selector
Clock Generator Module (CGM)
8.4.8 Base Clock
Advance Information
and
Circuit.)
CGM Registers
8.4.6
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