XC68HC08KH12 Motorola, XC68HC08KH12 Datasheet - Page 109
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XC68HC08KH12
Manufacturer Part Number
XC68HC08KH12
Description
MICROCONTROLLER
Manufacturer
Motorola
Datasheet
1.XC68HC08KH12.pdf
(262 pages)
- Current page: 109 of 262
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8.9.2 Parametric Influences on Reaction Time
MC68HC(7)08KH12
MOTOROLA
—
Rev. 1.0
Other systems refer to acquisition and lock times as the time the system
takes to reduce the error between the actual output and the desired
output to within specified tolerances. Therefore, the acquisition or lock
time varies according to the original error in the output. Minor errors may
not even be registered. Typical PLL applications prefer to use this
definition because the system requires the output frequency to be within
a certain tolerance of the desired frequency regardless of the size of the
initial error.
The discrepancy in these definitions makes it difficult to specify an
acquisition or lock time for a typical PLL. Therefore, the definitions for
acquisition and lock times for this module are:
Obviously, the acquisition and lock times can vary according to how
large the frequency error is and may be shorter or longer in many cases.
Acquisition and lock times are designed to be as short as possible while
still providing the highest possible stability. These reaction times are not
constant, however. Many factors directly and indirectly affect the
acquisition time.
•
•
Acquisition time, t
between the actual output frequency and the desired output
frequency to less than the tracking mode entry tolerance,
Acquisition time is based on an initial frequency error,
(f
bandwidth control mode (See
Bandwidth
becomes set in the PLL bandwidth control register (PBWC).
Lock time, t
between the actual output frequency and the desired output
frequency to less than the lock mode entry tolerance,
time is based on an initial frequency error, (f
more than 100 percent. In automatic bandwidth control mode,
lock time expires when the LOCK bit becomes set in the PLL
bandwidth control register (PBWC). (See
Automatic PLL Bandwidth
DES
Clock Generator Module (CGM)
– f
ORIG
)/f
LOCK
Modes.), acquisition time expires when the ACQ bit
DES
, is the time the PLL takes to reduce the error
, of not more than 100 percent. In automatic
ACQ
, is the time the PLL takes to reduce the error
Modes.)
8.4.5 Manual and Automatic PLL
Acquisition/Lock Time Specifications
Clock Generator Module (CGM)
8.4.5 Manual and
DES
– f
Advance Information
ORIG
)/f
LOCK
DES
, of not
. Lock
TRK
109
.
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