XC68HC08KH12 Motorola, XC68HC08KH12 Datasheet - Page 172

• Manufacturer Part Number: XC68HC08KH12
• Description: MICROCONTROLLER
• Manufacturer: Motorola

Timer Interface Module (TIM)
11.7 TIM During Break Interrupts
11.8 I/O Signals
11.8.1 TIM Clock Pin (PTE0/TCLK)
Advance Information
172
If TIM functions are not required during wait mode, reduce power
consumption by stopping the TIM before executing the WAIT instruction.
A break interrupt stops the TIM counter.
The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the break flag control register (BFCR) enables software to clear status
bits during the break state.
(BFCR).)
To allow software to clear status bits during a break interrupt, write a
logic one to the BCFE bit. If a status bit is cleared during the break state,
it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a logic zero to the
BCFE bit. With BCFE at logic zero (its default state), software can read
and write I/O registers during the break state without affecting status
bits. Some status bits have a two-step read/write clearing procedure. If
software does the first step on such a bit before the break, the bit cannot
change during the break state as long as BCFE is at logic zero. After the
break, doing the second step clears the status bit.
Port E shares three of its pins with the TIM. PTE0/TCLK is and external
clock input to the TIM prescaler. The two TIM channel I/O pins are
PTE1/TCH0 and PTE2/TCH1.
PTE0/TCLK is an external clock input that can be the clock source for
the TIM counter instead of the prescaled internal bus clock. Select the
PTE0/TCLK input by writing logic ones to the three prescaler select bits,
PS[2:0].
(See 11.9.1 TIM Status and Control Register
Timer Interface Module (TIM)
(See 7.8.3 Break Flag Control Register
MC68HC(7)08KH12
(TSC).) The
MOTOROLA
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Rev. 1.0