XC68HC08KH12 Motorola, XC68HC08KH12 Datasheet - Page 244

• Manufacturer Part Number: XC68HC08KH12
• Description: MICROCONTROLLER
• Manufacturer: Motorola

Break Module (BREAK)
16.4.1 Flag Protection During Break Interrupts
16.4.2 CPU During Break Interrupts
16.4.3 TIM During Break Interrupts
16.4.4 COP During Break Interrupts
16.5 Break Module Registers
Advance Information
244
The system integration module (SIM) controls whether or not module
status bits can be cleared during the break state. The BCFE bit in the
break flag control register (BFCR) enables software to clear status bits
during the break state. (See
(BFCR)
The CPU starts a break interrupt by:
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
A break interrupt stops the timer counter.
The COP is disabled during a break interrupt when V
on the RST pin.
Three registers control and monitor operation of the break module:
•
•
•
•
•
Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD
in monitor mode)
Break status and control register (BRKSCR)
Break address register high (BRKH)
Break address register low (BRKL)
and see the Break Interrupts subsection for each module.)
Break Module (BREAK)
7.8.3 Break Flag Control Register
MC68HC(7)08KH12
DD
+ V
HI
MOTOROLA
is present
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Rev. 1.0