XC68HC08KH12 Motorola, XC68HC08KH12 Datasheet - Page 175
XC68HC08KH12
Manufacturer Part Number
XC68HC08KH12
Description
MICROCONTROLLER
Manufacturer
Motorola
Datasheet
1.XC68HC08KH12.pdf
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11.9.2 TIM Counter Registers (TCNTH:TCNTL)
MC68HC(7)08KH12
MOTOROLA
NOTE:
NOTE:
—
Rev. 1.0
Do not set the TSTOP bit before entering wait mode if the TIM is required
to exit wait mode.
TRST — TIM Reset Bit
Setting the TSTOP and TRST bits simultaneously stops the TIM counter
at a value of $0000.
PS[2:0] — Prescaler Select Bits
The two read-only TIM counter registers contain the high and low bytes
of the value in the TIM counter. Reading the high byte (TCNTH) latches
the contents of the low byte (TCNTL) into a buffer. Subsequent reads of
PS2
Setting this write-only bit resets the TIM counter and the TIM
prescaler. Setting TRST has no effect on any other registers.
Counting resumes from $0000. TRST is cleared automatically after
the TIM counter is reset and always reads as logic zero. Reset clears
the TRST bit.
These read/write bits select either the PTE0/TCLK pin or one of the
seven prescaler outputs as the input to the TIM counter as
shows. Reset clears the PS[2:0] bits.
0
0
0
0
1
1
1
1
1 = Prescaler and TIM counter cleared
0 = No effect
PS1
0
0
1
1
0
0
1
1
Timer Interface Module (TIM)
PS0
0
1
0
1
0
1
0
1
Table 11-2. Prescaler Selection
Internal Bus Clock ÷ 1
Internal Bus Clock ÷ 2
Internal Bus Clock ÷ 4
Internal Bus Clock ÷ 8
Internal Bus Clock ÷ 16
Internal Bus Clock ÷ 32
Internal Bus Clock ÷ 64
TIM Clock Source
PTE0/TCLK
Timer Interface Module (TIM)
Advance Information
Table 11-2
I/O Registers
175
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