XC68HC08KH12 Motorola, XC68HC08KH12 Datasheet - Page 112
XC68HC08KH12
Manufacturer Part Number
XC68HC08KH12
Description
MICROCONTROLLER
Manufacturer
Motorola
Datasheet
1.XC68HC08KH12.pdf
(262 pages)
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Clock Generator Module (CGM)
Advance Information
112
NOTE:
an initial frequency error, (f
percent.
The inverse proportionality between the lock time and the reference
frequency.
In automatic bandwidth control mode, the acquisition and lock times are
quantized into units based on the reference frequency. (See
Manual and Automatic PLL Bandwidth
clock cycles, n
tracking mode entry tolerance,
certain number of clock cycles, n
is within the lock mode entry tolerance,
time, t
time, t
In manual mode, it is usually necessary to wait considerably longer than
t
Selector
Influences on Reaction Time
Automatic bandwidth mode is recommended for most users.
LOCKMAX
ACQ
AL
, is an integer multiple of n
before selecting the PLL clock (See
, is an integer multiple of n
Circuit.), because the factors described in
Clock Generator Module (CGM)
ACQ
, is required to ascertain that the PLL is within the
t
LOCKMAX
t
ACQ
DES
t
AL
=
=
=
– f
may slow the lock time considerably.
t
TRK
TRK
ACQ
ORIG
V
------------ -
V
------------ -
f
f
RDV
RDV
DDA
DDA
TRK
, is required to ascertain that the PLL
, before exiting acquisition mode. A
ACQ
+
)/f
/f
t
AL
RDV
DES
/f
------------ -
K
----------- -
K
RDV
+
ACQ
TRK
LOCK
4
8
, of not more than 100
.
256t
Modes.) A certain number of
, and the acquisition to lock
. Therefore, the acquisition
8.4.8 Base Clock
MC68HC(7)08KH12
VRDV
8.9.2 Parametric
MOTOROLA
8.4.5
—
Rev. 1.0
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