XC68HC08KH12 Motorola, XC68HC08KH12 Datasheet - Page 171

• Manufacturer Part Number: XC68HC08KH12
• Description: MICROCONTROLLER
• Manufacturer: Motorola

11.5 Interrupts
11.6 Wait Mode
MC68HC(7)08KH12
MOTOROLA
—
Rev. 1.0
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially
control the buffered PWM output. TIM status control register 0 (TSCR0)
controls and monitors the PWM signal from the linked channels. MS0B
takes priority over MS0A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM
overflows. Subsequent output compares try to force the output to a state
it is already in and have no effect. The result is a 0% duty cycle output.
Setting the channel x maximum duty cycle bit (CHxMAX) and clearing
the TOVx bit generates a 100% duty cycle output. See
Channel Status and Control Registers
The following TIM sources can generate interrupt requests:
The WAIT instruction puts the MCU in low-power-consumption standby
mode.
The TIM remains active after the execution of a WAIT instruction. In wait
mode the TIM registers are not accessible by the CPU. Any enabled
CPU interrupt request from the TIM can bring the MCU out of wait mode.
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•
TIM overflow flag (TOF) — The TOF bit is set when the TIM
counter value rolls over to $0000 after matching the value in the
TIM counter modulo registers. The TIM overflow interrupt enable
bit, TOIE, enables TIM overflow CPU interrupt requests. TOF and
TOIE are in the TIM status and control register.
TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an
input capture or output compare occurs on channel x. Channel x
TIM CPU interrupt requests are controlled by the channel x
interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests
are enabled when CHxIE=1. CHxF and CHxIE are in the TIM
channel x status and control register.
Timer Interface Module (TIM)
(TSC0:TSC1).
Timer Interface Module (TIM)
Advance Information
11.9.4 TIM
Interrupts
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