XC68HC08KH12 Motorola, XC68HC08KH12 Datasheet - Page 179

• Manufacturer Part Number: XC68HC08KH12
• Description: MICROCONTROLLER
• Manufacturer: Motorola

MC68HC(7)08KH12
MOTOROLA
NOTE:
—
Rev. 1.0
MSxB — Mode Select Bit B
MSxA — Mode Select Bit A
Before changing a channel function by writing to the MSxB or MSxA bit,
set the TSTOP and TRST bits in the TIM status and control register
(TSC).
ELSxB and ELSxA — Edge/Level Select Bits
This read/write bit selects buffered output compare/PWM operation.
MSxB exists only in the TIM channel 0 status and control register.
Setting MS0B disables the channel 1 status and control register and
reverts TCH1 to general-purpose I/O.
Reset clears the MSxB bit.
When ELSxB:A
operation or unbuffered output compare/PWM operation.
See
When ELSxB:A = 00, this read/write bit selects the initial output level
of the TCHx pin.
When channel x is an input capture channel, these read/write bits
control the active edge-sensing logic on channel x.
When channel x is an output compare channel, ELSxB and ELSxA
control the channel x output behavior when an output compare
occurs.
When ELSxB and ELSxA are both clear, channel x is not connected
to port E, and pin PTEx/TCHx is available as a general-purpose I/O
pin.
ELSxB and ELSxA bits.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
1 = Initial output level low
0 = Initial output level high
Table 11-3
Table
Timer Interface Module (TIM)
11-3.
shows how ELSxB and ELSxA work. Reset clears the
(See Table
00, this read/write bit selects either input capture
11-3.). Reset clears the MSxA bit.
Timer Interface Module (TIM)
Advance Information
I/O Registers
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