C8051F410DK Silicon Laboratories Inc, C8051F410DK Datasheet - Page 165

• Manufacturer Part Number: C8051F410DK
• Description: KIT DEV FOR C8051F41X
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F410DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F41x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F410
• Silicon Family Name: C8051F41x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F41x
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1314

19. Oscillators
C8051F41x devices include a programmable internal oscillator, an external oscillator drive circuit, and a
Clock Multiplier. The internal oscillator can be enabled/disabled and calibrated using the OSCICN and
OSCICL registers, as shown in Figure 19.1. The system clock (SYSCLK) can be derived from the internal
oscillator, external oscillator circuit, or smaRTClock oscillator. The clock multiplier can produce three possi-
ble base outputs which can be scaled by a programmable factor of 1, 2/3, 2/4 (or 1/2), 2/5, 2/6 (or 1/3), or
2/7: Internal Oscillator x 2, External Oscillator x 2, or External Oscillator x 4. Oscillator electrical specifica-
tions are given in Table 19.1 on page 175.
19.1. Programmable Internal Oscillator
All C8051F41x devices include a programmable internal oscillator that defaults as the system clock after a
system reset. The internal oscillator period can be programmed via the OSCICL register, shown in SFR
Definition 19.2. On C8051F41x devices, OSCICL is factory calibrated to obtain a 24.5 MHz frequency.
Electrical specifications for the precision internal oscillator are given in Table 19.1 on page 175. Note that
the system clock may be derived from the programmed internal oscillator divided by 1, 2, 4, 8, 16, 32, 64,
or 128 as defined by the IFCN bits in register OSCICN. The divide value defaults to 128 following a reset.
VDD
Option 2
XTAL2
Option 1
Option 4
10M
XTAL2
Option 3
XTAL2
XTAL1
XTAL2
Figure 19.1. Oscillator Diagram
OSCICL
Circuit
Input
Programmable
Internal Clock
Generator
OSCXCN
OSC
EN
Rev. 1.1
EXOSC / 2
OSCICN
IOSC
EXOSC
EXOSC
IOSC/2
IOSC
CLKMUL
n
Clock Multiplier
x4
C8051F410/1/2/3
n
smaRTClock
Oscillator
CLKSEL
SYSCLK
165