C8051F410DK Silicon Laboratories Inc, C8051F410DK Datasheet - Page 196

• Manufacturer Part Number: C8051F410DK
• Description: KIT DEV FOR C8051F41X
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F410DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F41x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F410
• Silicon Family Name: C8051F41x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051F41x
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1314

C8051F410/1/2/3
Figure 21.4 shows the typical SCL generation described by Equation 21.2. Notice that T
twice as large as T
extended low by slower slave devices, or driven low by contending master devices). The bit rate when
operating as a master will never exceed the limits defined by equation Equation 21.1.
Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA
setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high.
The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable
after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times
meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 21.2 shows the min-
imum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically
necessary when SYSCLK is above 10 MHz.
Note: For SCL operation above 100 kHz, EXTHOLD should be cleared to ‘0’.
With the SMBTOE bit set, Timer 3 should be configured to overflow after 25 ms in order to detect SCL low
timeouts (see
to reload while SCL is high, and allow Timer 3 to count when SCL is low. The Timer 3 interrupt service rou-
tine should be used to reset SMBus communication by disabling and re-enabling the SMBus.
SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will
be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see
Figure 21.4). When a Free Timeout is detected, the interface will respond as if a STOP was detected (an
interrupt will be generated, and STO will be set). Enabling the Bus Free Timeout is recommended.
196
Timer Source
*Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. The s/w delay occurs
Overflows
EXTHOLD
SCL
between the time SMB0DAT or ACK is written and when SI is cleared. Note that if SI is cleared in
the same write that defines the outgoing ACK value, s/w delay is zero.
0
1
Section “21.3.3. SCL Low Timeout” on page 194
LOW
Table 21.2. Minimum SDA Setup and Hold Times
T
. The actual SCL output may vary due to other devices on the bus (SCL may be
Low
Figure 21.4. Typical SMBus SCL Generation
Minimum SDA Setup Time
1 system clock + s/w delay*
T
low
11 system clocks
- 4 system clocks
T
OR
High
Rev. 1.1
). The SMBus interface will force Timer 3
Minimum SDA Hold Time
SCL High Timeout
12 system clocks
3 system clocks
HIGH
is typically