C8051F046-GQ Silicon Laboratories Inc, C8051F046-GQ Datasheet - Page 233

IC 8051 MCU 32K FLASH 100TQFP

C8051F046-GQ

Manufacturer Part Number
C8051F046-GQ
Description
IC 8051 MCU 32K FLASH 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F04xr
Datasheets

Specifications of C8051F046-GQ

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
64
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
CAN, SMBus, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
64
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F040DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 13 Channel
On-chip Dac
12 bit, 2 Channel
Package
100TQFP
Device Core
8051
Family Name
C8051F04x
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
336-1211

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Part Number
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Part Number:
C8051F046-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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Part Number:
C8051F046-GQR
Manufacturer:
Silicon Laboratories Inc
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CAN Register
Index
0x0A
0x0B
0x0C
0x0D
0x0E
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x08
0x09
0x0F
0x10
0x12
0x20
0x21
0x22
0x23
0x24
0x25
0x11
CAN Control Register
Status Register
Error Register
Bit Timing Register
Interrupt Register
Test Register
BRP Extension Register
IF1 Command Request
IF1 Command Mask
IF1 Mask 1
IF1 Mask 2
IF1 Arbitration 1
IF1 Arbitration 2
IF1 Message Control
IF1 Data A1
IF1 Data A2
IF1 Data B1
IF1 Data B2
IF2 Command Request
IF2 Command Mask
IF2 Mask 1
IF2 Mask 2
IF2 Arbitration 1
IF2 Arbitration 2
Table 18.2. CAN Register Index and Reset Values
Register Name
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0x0001
0x0000
0x0000
0x2301
0x0000
0x0000
0x0000
0x0001
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0001
0x0000
0x0000
0x0000
Reset
Value
Rev. 1.5
C8051F040/1/2/3/4/5/6/7
Accessible in CIP-51 SFR Map
Accessible in CIP-51 SFR Map
Read Only
Write Enabled by CCE Bit in CAN0CN
Read Only
Bit 7 (RX) is determined by CAN bus
Write Enabled by TEST bit in CAN0CN
CAN0ADR autoincrements in IF1 index space
(0x08 - 0x12) upon write to CAN0DATL
CAN0ADR autoincrement upon write to
CAN0DATL
CAN0ADR autoincrement upon write to
CAN0DATL
CAN0ADR autoincrement upon write to
CAN0DATL
CAN0ADR autoincrement upon write to
CAN0DATL
CAN0ADR autoincrement upon write to
CAN0DATL
CAN0ADR autoincrement upon write to
CAN0DATL
CAN0ADR autoincrement upon write to
CAN0DATL
CAN0ADR autoincrement upon write to
CAN0DATL
CAN0ADR autoincrement upon write to
CAN0DATL
CAN0ADR autoincrement upon write to
CAN0DATL
CAN0ADR autoincrements in IF2 index space
(0x20 - 0x2A) upon write to CAN0DATL
CAN0ADR autoincrement upon write to
CAN0DATL
CAN0ADR autoincrement upon write to
CAN0DATL
CAN0ADR autoincrement upon write to
CAN0DATL
CAN0ADR autoincrement upon write to
CAN0DATL
CAN0ADR autoincrement upon write to
CAN0DATL
Notes
233

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