C8051F046-GQ Silicon Laboratories Inc, C8051F046-GQ Datasheet - Page 76

• Manufacturer Part Number: C8051F046-GQ
• Description: IC 8051 MCU 32K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F04xr

Specifications of C8051F046-GQ

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: CAN, SMBus, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 64
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F040DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• On-chip Dac: 12 bit, 2 Channel
• Package: 100TQFP
• Device Core: 8051
• Family Name: C8051F04x
• Maximum Speed: 25 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1211

C8051F040/1/2/3/4/5/6/7
6.3.
ADC0 has a maximum conversion speed of 100 ksps. The ADC0 conversion clock is derived from the sys-
tem clock divided by the value held in the ADC0SC bits of register ADC0CF.
6.3.1. Starting a Conversion
A conversion can be initiated in one of four ways, depending on the programmed states of the ADC0 Start
of Conversion Mode bits (AD0CM1, AD0CM0) in ADC0CN. Conversions may be initiated by the following:
The AD0BUSY bit is set to logic 1 during conversion and restored to logic 0 when conversion is complete.
The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the AD0INT interrupt flag
(ADC0CN.5). Converted data is available in the ADC0 data word MSB and LSB registers, ADC0H, ADC0L.
Converted data can be either left or right justified in the ADC0H:ADC0L register pair (see example in
Figure 6.7) depending on the programmed state of the AD0LJST bit in the ADC0CN register.
When initiating conversions by writing a ‘1’ to AD0BUSY, the AD0INT bit should be polled to determine
when a conversion has completed (ADC0 interrupts may also be used). The recommended polling proce-
dure is shown below.
6.3.2. Tracking Modes
According to Table 6.2, each ADC0 conversion must be preceded by a minimum tracking time for the con-
verted result to be accurate. The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode.
In its default state, the ADC0 input is continuously tracked when a conversion is not in progress. When the
AD0TM bit is logic 1, ADC0 operates in low-power tracking mode. In this mode, each conversion is pre-
ceded by a tracking period of 3 SAR clocks after the start-of-conversion signal. When the CNVSTR0 signal
is used to initiate conversions in low-power tracking mode, ADC0 tracks only when CNVSTR0 is low; con-
version begins on the rising edge of CNVSTR0 (see Figure 6.4). Tracking can also be disabled when the
entire chip is in low power standby or sleep modes. Low-power tracking mode is also useful when AMUX
or PGA settings are frequently changed, to ensure that settling time requirements are met (see
“6.3.3. Settling Time Requirements” on page
76
ADC Modes of Operation
• Writing a ‘1’ to the AD0BUSY bit of ADC0CN;
• A Timer 3 overflow (i.e., timed continuous conversions);
• A rising edge detected on the external ADC convert start signal, CNVSTR0;
• A Timer 2 overflow (i.e., timed continuous conversions).
Step 1. Write a ‘0’ to AD0INT;
Step 2. Write a ‘1’ to AD0BUSY;
Step 3. Poll AD0INT for ‘1’;
Step 4. Process ADC0 data.
78).
Rev. 1.5
Section