MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 134

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Cache Organization
Figure 4-4. Data Cache—A: at Reset, B: after Invalidation, C and D: Loading Pattern
Set 127
4-10
Set 0
A:Cache population at
At reset, cache contents
are indeterminate; V and
M may be set. The cache
should be cleared
explicitly by setting
CACR[DCINVA] before
the cache is enabled.
Way 0 Way 1 Way 2 Way 3
start-up
Invalid (V = 0)
Valid, not modified (V = 1, M = 0)
Valid, modified (V = 1, M = 1)
B:Cache after invalidation,
Setting CACR[DCINVA]
invalidates the entire
cache.
Way 0 Way 1 Way 2 Way 3
before it is enabled
MCF5407 User’s Manual
C:Cache after loads in
Initial cacheable
accesses to memory-fill
positions in way 0.
Way 0 Way 1 Way 2 Way 3
Way 0
D:First load in Way 1
A line is loaded in
way 1 only if that set is
full in way 0.
Way 0 Way 1 Way 2 Way 3