MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 223

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.2.6 Software Watchdog Interrupt Vector Register (SWIVR)
The SWIVR, shown in Figure 6-6, contains the 8-bit interrupt vector (SWIV) that the SIM
returns during an interrupt-acknowledge cycle in response to a software watchdog
timer-generated interrupt. SWIVR is set to the uninitialized vector 0x0F at system reset.
Note that the software watchdog interrupt cannot be autovectored.
6.2.7 Software Watchdog Service Register (SWSR)
The SWSR, shown in Figure 6-7, is where the software watchdog timer servicing sequence
should be written. To prevent a watchdog timer timeout, the software service sequence must
be performed (0x55 followed by 0xAA written to the SWSR). Both writes must be
performed in order before the timeout, but any number of instructions or accesses to the
SWSR can be executed between the two writes. If the timer has timed out, writing to SWSR
does not cancel the interrupt (that is, IPR[SWT] remains set). The interrupt is cancelled
(and SWT is cleared) automatically when the IACK cycle is run.
Bits
2
1
SWTAVAL Software watchdog transfer acknowledge valid
Name
SWTA
Address
Address
Figure 6-6. Software Watchdog Interrupt Vector Register (SWIVR)
Reset
Reset
Field
Field
R/W
R/W
Figure 6-7. Software Watchdog Service Register (SWSR)
Software watchdog transfer acknowledge enable
0 SWTA transfer acknowledge disabled
1 SWTA asserts transfer acknowledge enabled. After one timeout period of the unacknowledged
0 SWTA transfer acknowledge has not occurred.
1 SWTA transfer acknowledge has occurred. Write a 1 to clear this flag bit.
assertion of the software watchdog timer interrupt, the software watchdog transfer
acknowledge asserts, which allows the watchdog timer to terminate a bus cycle and allow the
IACK to occur.
Table 6-4. SYPCR Field Descriptions (Continued)
7
7
Chapter 6. SIM Overview
Supervisor write only
Supervisor write only
MBAR + 0x002
MBAR + 0x003
Undetermined
0000_1111
SWSR
SWIV
Description
Programming Model
0
0
6-9