MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 148

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Cache Management
Table 4-5 describes ACRn fields.
4.11 Cache Management
The cache can be enabled and configured by using a MOVEC instruction to access CACR.
A hardware reset clears CACR, disabling the cache and removing all configuration
information; however, reset does not affect the tags, state information, and data in the cache.
Set CACR[DCINVA,ICINVA] to invalidate the caches before enabling them.
4-24
Reset
31–24
23–16
15
14–13
12–7
6–5
4–3
2
1–0
Field
R/W
I
Bits
Rc
1
31
Reserved in ACR2 and ACR3.
Address
Address
Name
mask
base
CM
—
—
—
W
E
S
Address Base
Address base. Compared with address bits A[31:24]. Eligible addresses that match are
assigned the access control attributes of this register.
Address mask. Setting a mask bit causes the corresponding address base bit to be ignored.
The low-order mask bits can be set to define contiguous regions larger than 16 Mbytes. The
mask can define multiple noncontiguous regions of memory.
Enable. Enables or disables the other ACRn bits.
0 Access control attributes disabled
1 Access control attributes enabled
Supervisor mode. Specifies whether only user or supervisor accesses are allowed in this
address range or if the type of access is a don’t care.
00 Match addresses only in user mode
01 Match addresses only in supervisor mode
1x Execute cache matching on all accesses
Reserved; should be cleared.
Cache mode. Selects the cache mode and access precision. Precise and imprecise modes are
described in Section 4.9.2, “Cache-Inhibited Accesses.”
00 Cacheable, write-through
01 Cacheable, copyback
10 Cache-inhibited, precise
11 Cache-inhibited, imprecise
Reserved, should be cleared.
ACR0/ACR1 only. Write protect. Selects the write privilege of the memory region. ACR2[2] and
ACR3[2] are reserved.
0 Read and write accesses permitted
1 Write accesses not permitted
Reserved, should be cleared.
Figure 4-9. Access Control Register Format (ACRn)
Uninitialized
24 23
Table 4-5. ACRn Field Descriptions
ACR0: 0x004; ACR1: 0x005; ACR2: 0x006; ACR3: 0x007
Address Mask
MCF5407 User’s Manual
Write (R/W by debug module)
16 15 14 13 12
Description
E
0
S
—
Uninitialized
7
6
CM
5
4
—
3
W
2
1
1
—
0