MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 297

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Accesses in synchronous burst page mode always cause the following sequence:
11.4.4.4 Continuous Page Mode
Continuous page mode is identical to burst page mode, except that it allows the processor
core to handle successive bus cycles that hit the same page without having to close the page.
When the current bus cycle finishes, the MCF5407 core internal pipelined bus can predict
whether the upcoming cycle will hit in the same page.
RAS[0] or [1]
1.
2.
3. Required number of
4. Some transfers need more
5.
6. Required number of idle clocks inserted to assure precharge-to-
• If the next bus cycle is not pending or misses in the page, the
CAS[3:0]
DRAMW
D[31:0]
A[31:0]
CLKIN
SRAS
SCAS
ACTV
NOP
NOP
given port size.
PALL
generated to the SDRAM.
commands to assure SRAS-to-SCAS delay (if CAS latency is 1, there are no
commands).
command
command
ACTV
t
CASL
Chapter 11. Synchronous/Asynchronous DRAM Controller Module
Row
= 2
NOP
Figure 11-19. Burst Write SDRAM Access
READ
Column
NOP
or
WRITE
Column
commands to assure the
WRITE
commands to service the transfer size with the
Column
t
RWL
NOP
Column
ACTV
PALL
-to-precharge delay.
Synchronous Operation
PALL
ACTV
t
command is
RP
delay.
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