MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 300

IC MPU 32B 220MHZ COLDF 208-FQFP

MCF5407AI220

Manufacturer Part Number
MCF5407AI220
Description
IC MPU 32B 220MHZ COLDF 208-FQFP
Manufacturer
Freescale Semiconductor
Series
MCF540xr
Datasheets

Specifications of MCF5407AI220

Core Processor
Coldfire V4
Core Size
32-Bit
Speed
220MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-FQFP
Maximum Clock Frequency
220 MHz
Operating Supply Voltage
1.8 V, 3.3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Program Memory Size
24KB
Cpu Speed
220MHz
Embedded Interface Type
I2C, UART
Digital Ic Case Style
FQFP
No. Of Pins
208
Supply Voltage Range
3.3V
Rohs Compliant
Yes
For Use With
M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF5407AI220
Manufacturer:
freescaie
Quantity:
6
Part Number:
MCF5407AI220
Manufacturer:
Freescale Semiconductor
Quantity:
135
Part Number:
MCF5407AI220
Manufacturer:
FREESCALE
Quantity:
1 831
Part Number:
MCF5407AI220
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MCF5407AI220
Manufacturer:
NXP
Quantity:
25
Synchronous Operation
11.4.4.6 Self-Refresh Operation
Self-refresh is a method of allowing the SDRAM to enter into a low-power state, while at
the same time to perform an internal refresh operation and to maintain the integrity of the
data stored in the SDRAM. The DRAM controller supports self-refresh with DCR[IS].
When IS is set, the
command is sent to the DRAM controller. Figure 11-23 shows the self-refresh operation.
11.4.5 Initialization Sequence
Synchronous DRAMs have a prescribed initialization sequence. The DRAM controller
(DCR[COC] = 0)
11-32
RAS[0] or [1]
RAS[0] or [1]
DRAMW
A[31:0]
DRAMW
CLKIN
SRAS
SCAS
CLKIN
SRAS
SCAS
SCKE
PALL
PALL
SELF
t
t
RCD
NOP
RCD
NOP
= 2
Figure 11-22. Auto-Refresh Operation
= 2
Figure 11-23. Self-Refresh Operation
command is sent to the SDRAM. When IS is cleared, the
SELF
REF
Refresh
MCF5407 User’s Manual
Active
Self-
SELFX
t
RC
NOP
t
RC
= 6
= 6
NOP
Possible
ACTV
ACTV
First
SELFX

Related parts for MCF5407AI220