MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 517

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The results of all PC breakpoint registers, PBR/PBMR, PBR1, PBR2, and PBR3, are
logically summed to form a single PC breakpoint trigger signal.
A.8.3.4 Data Breakpoint Register 1 (DBR1, DBMR1)
The data breakpoint register 1 (DBR1) defines a specific data pattern that can be used as
part of a trigger. The DBR1 value is masked by DBMR1, allowing only those bits in DBR1
that have a corresponding zero in DBMR1 to be compared with the ColdFire CPU core data
signals, as defined in the TDR and the XTDR.
The data breakpoint registers support both aligned and misaligned operand references. The
relationship between the processor core address, the access size, and the corresponding
location within the 32-bit core data bus is defined in the DBR and DBMR description.
A.8.3.5 Extended Trigger Definition Register (XTDR)
The XTDR enables the operation as defined by the new breakpoint registers, ABHR1,
ABLR1, AATR1, DBR1, and DBMR1, within the debug module and operates in
conjunction with the trigger definition register (TDR). The added breakpoint logic can be
included as a one- or two-level trigger; XTDR[29–18] define second-level triggers and
XTDR[13–2] define first-level triggers. The definition of the XTDR register is exactly the
same as the TDR for the control of the ABHR1, ABLR1, DBR1 and DBMR1 breakpoint
registers. The XTDR is cleared on reset. For more details about this register see
Section 5.4.8, “Extended Trigger Definition Register (XTDR)”.
A.8.4 Debug Interrupt Exception Vectors
In the Debug B revision, if the occurrence of a hardware breakpoint is configured to
generate a debug interrupt, this exception is mapped to vector number 12 (0x030). The
actual debug interrupts can be broadly classified into two groups—PC breakpoints and all
other types. A PC breakpoint is treated in a precise manner—exception recognition and
processing are initiated before the instruction at the given address is executed. Conversely,
all other breakpoint events are recognized on the given internal bus transaction, but are
made pending to the processor and sampled like other interrupt conditions. As a result,
these types of interrupts are imprecise by nature.
In response to a customer request that PC breakpoints be distinguishable from other type
of trigger events, the debug interrupt exception vector is expanded in Debug C of the
MCF5407 to two unique entries, shown in Table A-12, where the occurrence of a PC
breakpoint generates the 0x034 vector. In the case of a two-level trigger, the last breakpoint
event determines the exception vector.
• PBRn[31:1] = program counter breakpoint address
• PBRn[0] = valid bit
Appendix A. Migrating from the ColdFire MCF5307 to the MCF5407
Revision C Debug
A-15