MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 209

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
2
3
4
Rn represents any {Dn, An} register. In this definition, the ‘y’ suffix generally denotes the
source and ‘x’ denotes the destination operand. For a given instruction, the optional
operand data is displayed only for those effective addresses referencing memory.
Exception Processing
The PSTDDATA specification for the reset exception is shown below:
Exception Processing
The initial references at address 0 and 4 are never captured nor displayed since these
accesses are treated as instruction fetches.
For all types of exception processing, the PSTDDATA = 0xC value is driven at all times,
unless the PSTDDATA output is needed for one of the optional marker values or for the
taken branch indicator (0x5).
5.8.2 Supervisor Instruction Set
The supervisor instruction set has complete access to the user mode instructions plus the
opcodes shown below. Table 5-28 shows the PSTDDATA specification for these opcodes.
tst.w
tst.l
unlk
wddata.b
wddata.w
wddata.l
For JMP and JSR instructions, the optional target instruction address is displayed only for those effective
address fields defining variant addressing modes. This includes the following <ea>x values: (An), (d16,An),
(d8,An,Xi), (d8,PC,Xi).
For move multiple instructions (MOVEM), the processor automatically generates line-sized transfers if the
address reaches a cache line (0-modulo-16) boundary four or more registers are to be transferred. For these
line-sized transfers, the operand data is never captured nor displayed, regardless of the CSR value.
Automatic line-sized burst transfers maximize performance for these sequential memory accesses.
The source operand in predicted RTS is displayed if CSR[12] and/or (CSR[9] or CSR[8]) is set.
During normal exception processing, PSTDDATA outputs are driven to 0xC. The exception stack write operands
and the vector read and target address of the exception handler may also be displayed.
Table 5-27. PSTDDATA Specification for User-Mode Instructions (Continued)
Instruction
PSTDDATA = C,{B, destination}, // stack frame
PSTDDATA = 5,{[9AB], target} // PC of handler
PSTDDATA = C,
PSTDDATA = 5,{[9AB], target} // initial PC
<ea>x
<ea>x
Ax
<ea>y
<ea>y
<ea>y
{B, destination},// stack frame
{B, source},// vector read
Syntax
Chapter 5. Debug Support
PSTDDATA = 1, {9, source operand}
PSTDDATA = 1, {B, source operand}
PSTDDATA = 1, {B, destination operand}
PSTDDATA = 4, 8, source operand
PSTDDATA = 4, 9, source operand
PSTDDATA = 4, B, source operand
Debug C Definition of PSTDDATA Outputs
PSTDDATA
5-53