MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 257

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Reset
Reset
Field
Field DMA1 DMA0 UART1 UART0 I2C TIMER2 TIMER1 SWT EINT7 EINT6 EINT5 EINT4 EINT3 EINT2 EINT1
Addr
R/W
R/W
Table 9-7 describes IPR and IMR fields.
9.2.4 Interrupt Port Assignment Register (IRQPAR)
The interrupt port assignment register (IRQPAR), shown in Figure 9-5, provides the level
assignment of the primary external interrupt pins—IRQ5, IRQ3, and IRQ1. The setting of
IRQPAR2–IRQPAR0 determines the interrupt level of these external interrupt pins.
Table 9-8 describes IRQPAR fields.
31–18
17–1
Address
Bits
Figure 9-4. Interrupt Pending Register (IPR) and Interrupt Mask Register (IMR)
Reset
31
15
Field IRQPAR2
R/W
Figure
Name
30
14
See
9-4
—
1111
7
Figure 9-5. Interrupt Port Assignment Register (IRQPAR)
29
13
Reserved, should be cleared.
Interrupt pending/mask. Each bit corresponds to an interrupt source defined by the ICR. The
corresponding IMR bit determines whether an interrupt condition can generate an interrupt. At
every clock, the IPR samples the signal generated by the interrupting source. The corresponding
IPR bit reflects the state of the interrupt signal even if the corresponding IMR bit is set.
0 The corresponding interrupt source is not masked (IMR) and has no interrupt pending (IPR).
1 The corresponding interrupt source is masked (IMR) and has an interrupt pending (IPR)
IRQPAR1
28
12
Table 9-7. IPR and IMR Field Descriptions
6
27
11
IRQPAR0
Chapter 9. Interrupt Controller
26
10
MBAR + 0x040 (IPR); + 0x044 (IMR)
5
1111
Read-only (IPR); R/W (IMR)
Read-only (IPR); R/W (IMR)
25
9
—
—
4
MBAR + 0x06
0000_0000
24
8
R/W
Description
23
7
—
3
22
6
1111
21
5
Interrupt Controller Registers
2
20
4
ENBDACK1 ENBDACK0
19
1
3
1
18
1
2
DMA3 DMA2
17
0
1
1
1
9-7
—
16
—
1
0