MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 303

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11.5.2 DCR Initialization
At power-up, the DCR has the following configuration if synchronous operation and
SDRAM address multiplexing is desired.
This configuration results in a value of 0x8026 for DCR, as shown in Table 11-34.
10–9
11.5.3 DACR Initialization
As shown in Figure 11-26, in this example the SDRAM is programmed to access only the
second 512-Kbyte block of each 1-Mbyte partition in the SDRAM (each 16 Mbytes). The
starting address of the SDRAM is 0xFF80_0000. Continuous page mode feature is used.
Bits
8–0
MCF5407
Pins
SDRAM
Pins
15
14
13
12
11
Setting
(hex)
Field SO
Name
RTIM
NAM
COC
SO
RC
—
IS
15
1
A15
A0
Setting
res
14
0x26
X
00
1
0
0
0
x
8
A14
NAM COC
A1
13
0
Chapter 11. Synchronous/Asynchronous DRAM Controller Module
Table 11-33. SDRAM Hardware Connections
Indicating synchronous operation
Don’t care (reserved)
Indicating SDRAM controller multiplexes address lines internally
SCKE is used as clock enable instead of command bit because user is not multiplexing
address lines externally and requires external command feed.
At power-up, allowing power self-refresh state is not appropriate because registers are
being set up.
Because t
Specification indicates auto-refresh period for 4096 rows to be 64 mS or refresh every
15.625 µs for each row, or 625 bus clocks at 40 MHz. Because DCR[RC] is incremented by
1 and multiplied by 16, RC = (625 bus clocks/16) -1 = 38.06 = 0x38
Figure 11-25. Initialization Values for DCR
A13
A2
12
Table 11-34. DCR Initialization Values
0
RC
A12
A3
11
IS
0
value is 70 nS, indicating a 3-clock refresh-to-
A11
10
A4
0
RTIM
0
A10
0
9
A5
0
8
A9
A6
0
Description
A17
A7
0
A18
A8
2
1
A19
A9
RC
0
ACTV
A10 = CMD
timing.
0
A20
SDRAM Example
1
6
BA0
A21
1
11-35
BA1
A22
0
0