MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 453

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 18-9. Cycles for External Master Burst Line Access to 32-Bit Port (Continued)
18.9.1 Two-Device Bus Arbitration Protocol (Two-Wire
Two-wire mode bus arbitration lets the MCF5407 share the external bus with a single
external bus device without requiring an external bus arbiter. Figure 18-26 shows the
MCF5407 connecting to an external device using the two-wire mode. The MCF5407 BG
input is connected to the HOLDREQ output of the external device; the MCF5407 BD
output is connected to the HOLDACK input of the external device. Because the external
device controls the state of HOLDREQ, it controls when the MCF5407 is granted the bus,
giving the MCF5407 lower priority.
When the external device is not using the bus, it negates HOLDREQ, driving BG low and
granting the bus to the MCF5407. When the MCF5407 has an internal bus request pending
and BG is low, the MCF5407 drives BD low, negating HOLDACK to the external device.
When the external bus device needs the external bus, it asserts HOLDREQ, driving BG
high, requesting the MCF5407 to release the bus. If BG is negated while a bus cycle is in
progress, the MCF5407 releases the bus at the completion of the bus cycle. Note that the
MCF5407 considers the individual transfers of a burst or burst-inhibited access to be a
single bus cycle and does not release the bus until the last transfer of the series completes.
When the bus has been granted to the MCF5407, one of two situations can occur. In the first
case, if the MCF5407 has an internal bus request pending, the MCF5407 asserts BD to
indicate explicit bus mastership and begins the pending bus cycle by asserting TS. As
C6–C8
Cycle
C9
Mode)
No-wait state data transfers 2–4 occur on the rising edges of CLKIN. TA continues to be asserted indicating
completion of each transfer. TIP, CSx, and BE/BWE[3:0] are driven.
TA negates on the rising edge of CLKIN along with external device’s negation of TIP. On the falling edge,
the MCF5407 negates chip select and byte enables, creating an opportunity for another cycle to begin.
Figure 18-26. MCF5407 Two-Wire Mode Bus Arbitration Interface
MCF5407
SIZ[1:0]
A[31:0]
D[31:0]
R/W
BG
BD
BR
TS
TA
To/from external memory and control
Chapter 18. Bus Operation
Definition
General Operation of External Master Transfers
HOLDREQ
HOLDACK
A[31:0]
D[31:0]
TS
R/W
SIZ[1:0]
TA
External Bus Master
18-25