MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 305

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11.5.4 DMR Initialization
In this example, again, only the second 512-Kbyte block of each 1-Mbyte space is accessed
in each bank. In addition the SDRAM component is mapped only to readable and writable
supervisor and user data. The DMRs have the following configuration.
With this configuration, the DMR0 = 0x0074_0075, as described in Table 11-36.
31–16
15–9
8
7
6
5
4
3
2
1
0
2
1–0
Bits
Setting
Setting
Bits
(hex)
(hex)
Field
Field
Name
BAM
WP
AM
SC
SD
UC
UD
C/I
—
—
V
31
15
0
X
Name
PM
—
Setting
X
0
0
1
1
1
0
1
0
1
Setting
0
0
1
X
0
Chapter 11. Synchronous/Asynchronous DRAM Controller Module
With bits 17 and 16 as don’t cares, BAM = 0x0074, which leaves bank select bits and
upper 512K select bits unmasked. Note that bits 22 and 21 are set because they are used
as bank selects; bit 20 is set because it controls the 1-Mbyte boundary address.
Reserved. Don’t care.
Allow reads and writes
Reserved
Disable CPU space access
Disable alternate master access
Disable supervisor code accesses
Enable supervisor data accesses
Disable user code accesses
Enable user data accesses
Enable accesses.
Table 11-35. DACR Initialization Values
Table 11-36. DMR0 Initialization Values
Indicates continuous page mode
Reserved. Don’t care.
—
X
0
Figure 11-28. DMR0 Register
0
X
X
0
0
0
X
0
9
BAM
WP
0
0
8
—
0
X
7
Description
Description
C/I
1
1
6
7
7
AM
1
1
5
SC
1
1
4
SD
0
3
0
SDRAM Example
UC
18
1
1
2
4
5
UD
17
X
0
1
—
11-37
16
X
V
1
0