MCF5407AI220 Freescale Semiconductor, MCF5407AI220 Datasheet - Page 21

• Manufacturer Part Number: MCF5407AI220
• Description: IC MPU 32B 220MHZ COLDF 208-FQFP
• Manufacturer: Freescale Semiconductor
• Series: MCF540xr

Specifications of MCF5407AI220

• Core Processor: Coldfire V4
• Core Size: 32-Bit
• Speed: 220MHz
• Connectivity: EBI/EMI, I²C, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-FQFP
• Maximum Clock Frequency: 220 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Program Memory Size: 24KB
• Cpu Speed: 220MHz
• Embedded Interface Type: I2C, UART
• Digital Ic Case Style: FQFP
• No. Of Pins: 208
• Supply Voltage Range: 3.3V
• Rohs Compliant: Yes
• For Use With: M5407C3 - KIT EVAL FOR MCF5407 W/ETHERNET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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Figure
Number
MCF5407 Block Diagram............................................................................................. 1-2
UART Module Block Diagram................................................................................... 1-10
PLL Module ................................................................................................................ 1-13
ColdFire MCF5407 Programming Model .................................................................. 1-15
ColdFire Enhanced Pipeline ......................................................................................... 2-3
ColdFire Multiply-Accumulate Functionality Diagram ............................................... 2-5
ColdFire Programming Model...................................................................................... 2-8
Condition Code Register (CCR) ................................................................................... 2-9
Status Register (SR).................................................................................................... 2-11
Vector Base Register (VBR)....................................................................................... 2-12
Organization of Integer Data Formats in Data Registers............................................ 2-13
Organization of Integer Data Formats in Address Registers ...................................... 2-14
Memory Operand Addressing..................................................................................... 2-14
Exception Stack Frame Form...................................................................................... 2-33
ColdFire MAC Multiplication and Accumulation........................................................ 3-2
MAC Programming Model ........................................................................................... 3-2
SRAM Base Address Registers (RAMBARn) ............................................................. 4-3
Data Cache Organization .............................................................................................. 4-7
Data Cache Organization and Line Format .................................................................. 4-8
Data Cache—A: at Reset, B: after Invalidation, C and D: Loading Pattern............... 4-10
Data Caching Operation.............................................................................................. 4-11
Write-Miss in Copyback Mode................................................................................... 4-16
Data Cache Locking.................................................................................................... 4-20
Cache Control Register (CACR) ................................................................................ 4-21
Access Control Register Format (ACRn) ................................................................... 4-24
An Format (Data Cache)............................................................................................. 4-25
An Format (Instruction Cache) ................................................................................... 4-25
Instruction Cache Line State Diagram........................................................................ 4-27
Data Cache Line State Diagram—Copyback Mode ................................................... 4-28
Data Cache Line State Diagram—Write-Through Mode ........................................... 4-29
Processor/Debug Module Interface............................................................................... 5-1
PSTCLK Timing........................................................................................................... 5-3
PSTDDATA: Single-Cycle Instruction Timing............................................................ 5-3
Example JMP Instruction Output on PSTDDATA....................................................... 5-6
Debug Programming Model ......................................................................................... 5-9
Address Attribute Trigger Registers (AATR, AATR1).............................................. 5-11
ILLUSTRATIONS
Illustrations
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