MC9S08GT60CFD Freescale Semiconductor, MC9S08GT60CFD Datasheet - Page 107

• Manufacturer Part Number: MC9S08GT60CFD
• Description: MCU 8BIT 60K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08GT60CFD

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

The ICG will remain in this state while the count error (∆n) is greater than the maximum n
the minimum n
In this state, the pulse counter, subtractor, digital loop filter, and DCO form a closed loop and attempt to
lock it according to their operational descriptions later in this section. Upon entering this state and until
the FLL becomes locked, the output clock signal ICGOUT frequency is given by f
extra divide by two prevents frequency overshoots during the initial locking process from exceeding
chip-level maximum frequency specifications. Once the FLL has locked, if an unexpected loss of lock
causes it to re-enter the unlocked state while the ICG remains in FEE mode, the output clock signal
ICGOUT frequency is given by f
7.3.5.2
FEE locked is entered from FEE unlocked when the count error (∆n) is less than n
than n
condition. The output clock signal ICGOUT frequency is given by f
locked, the filter value is only updated once every four comparison cycles. The update made is an average
of the error measurements taken in the four previous comparisons.
7.3.6
To determine the FLL locked and loss-of-lock conditions, the pulse counter counts the pulses of the DCO
for one comparison cycle (see
the subtractor. The subtractor compares this value to the value in MFD and produces a count error, ∆n. To
achieve locked status, ∆n must be between n
stay between n
the LOLS status bit is set and remains set until cleared by software or until the MCU is reset. LOLS is
cleared by reading ICGS1 then writing 1 to ICGIF (LOLRE = 0), or by a loss-of-lock induced reset
(LOLRE = 1), or by any MCU reset.
If the ICG enters the off state due to stop mode when ENBDM = OSCSTEN = 0, the FLL loses locked
status (LOCK is cleared), but LOLS remains unchanged because this is not an unexpected loss-of-lock
condition. Though it would be unusual, if ENBDM is cleared to 0 while the MCU is in stop, the ICG enters
the off state. Because this is an unexpected stopping of clocks, LOLS will be set when the MCU wakes up
from stop.
Expected loss of lock occurs when the MFD or CLKS bits are changed or in FEI mode only, when the
TRIM bits are changed. In these cases, the LOCK bit will be cleared until the FLL regains lock, but the
LOLS will not be set.
7.3.7
The reference clock and the DCO clock are monitored under different conditions (see
the reference frequency is being monitored, ERCS = 1 indicates that the reference clock meets minimum
frequency requirements. When the reference and/or DCO clock(s) are being monitored, if either one falls
below a certain frequency, f
LOCS will remain set until it is cleared by software or until the MCU is reset. LOCS is cleared by reading
Freescale Semiconductor
lock
(min) for a given number of samples, as required by the lock detector to detect the lock
FLL Lock and Loss-of-Lock Detection
FLL Loss-of-Clock Detection
FLL Engaged External Locked
unlock
lock
, as required by the lock detector to detect the lock condition.
(min) and n
LOR
Table 7-3
and f
unlock
ICGDCLK
LOD
MC9S08GB/GT Data Sheet, Rev. 2.3
(max) to remain locked. If ∆n goes outside this range unexpectedly,
for explanation of a comparison cycle) and passes this number to
, respectively, the LOCS status bit will be set to indicate the error.
/ R.
lock
(min) and n
lock
(max). Once the FLL has locked, ∆n must
ICGDCLK
/R. In FLL engaged external
ICGDCLK
lock
Table
(max) and greater
Functional Description
lock
7-2). Provided
/ (2×R) This
or less than
107