MC9S08GT60CFD

Manufacturer Part NumberMC9S08GT60CFD
DescriptionMCU 8BIT 60K FLASH 48-QFN
ManufacturerFreescale Semiconductor
SeriesHCS08
MC9S08GT60CFD datasheet
 

Specifications of MC9S08GT60CFD

Core ProcessorHCS08Core Size8-Bit
Speed40MHzConnectivityI²C, SCI, SPI
PeripheralsLVD, POR, PWM, WDTNumber Of I /o39
Program Memory Size60KB (60K x 8)Program Memory TypeFLASH
Ram Size4K x 8Voltage - Supply (vcc/vdd)1.8 V ~ 3.6 V
Data ConvertersA/D 8x10bOscillator TypeInternal
Operating Temperature-40°C ~ 85°CPackage / Case48-QFN Exposed Pad
Lead Free Status / RoHS StatusLead free / RoHS CompliantEeprom Size-
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Data Sheet
HCS08
Microcontrollers
MC9S08GB60/D
Rev. 2.3
12/2004
freescale.com

MC9S08GT60CFD Summary of contents

  • Page 1

    MC9S08GB60 MC9S08GB32 MC9S08GT60 MC9S08GT32 MC9S08GT16 Data Sheet HCS08 Microcontrollers MC9S08GB60/D Rev. 2.3 12/2004 freescale.com ...

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  • Page 3

    MC9S08GB/GT Data Sheet Covers: MC9S08GB60 MC9S08GB32 MC9S08GT60 MC9S08GT32 MC9S08GT16 MC9S08GB60 Rev. 2.3 12/2004 ...

  • Page 4

    ... Minor changes to Clarifications in 2.3 12/01/2004 and Status package (see This product incorporates SuperFlash Freescale‚ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2004. All rights reserved. 4 Description of Changes values to Electricals, appendix A DD Table A-9 and added a fi ...

  • Page 5

    ... Chapter 12 Serial Peripheral Interface (SPI) Module.............................. 187 Chapter 13 Inter-Integrated Circuit (IIC) Module .................................... 203 Chapter 14 Analog-to-Digital Converter (ATD) Module ......................... 219 Chapter 15 Development Support ........................................................... 235 Appendix A Electrical Characteristics...................................................... 259 Appendix B Ordering Information and Mechanical Drawings................ 281 Freescale Semiconductor MC9S08GB/GT Data Sheet, Rev. 2.3 5 ...

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  • Page 7

    ... Stop2 Mode ......................................................................................................................35 3.6.3 Stop3 Mode ......................................................................................................................36 3.6.4 Active BDM Enabled in Stop Mode ................................................................................36 3.6.5 LVD Enabled in Stop Mode .............................................................................................37 3.6.6 On-Chip Peripheral Modules in Stop Modes ...................................................................37 Freescale Semiconductor Contents Title Chapter 1 Introduction Chapter 2 Pins and Connections Chapter 3 Modes of Operation MC9S08GB/GT Data Sheet, Rev. 2.3 ...

  • Page 8

    ... Interrupt Vectors, Sources, and Local Masks ..................................................................65 5.6 Low-Voltage Detect (LVD) System ................................................................................................67 5.6.1 Power-On Reset Operation ..............................................................................................67 5.6.2 LVD Reset Operation .......................................................................................................67 5.6.3 LVD Interrupt Operation .................................................................................................67 5.6.4 Low-Voltage Warning (LVW) ..........................................................................................67 5.7 Real-Time Interrupt (RTI) ...............................................................................................................67 8 Title Chapter 4 Memory Chapter 5 MC9S08GB/GT Data Sheet, Rev. 2.3 Page Freescale Semiconductor ...

  • Page 9

    ... Port D Registers (PTDD, PTDPE, PTDSE, and PTDDD) ..............................................89 6.6.5 Port E Registers (PTED, PTEPE, PTESE, and PTEDD) ................................................90 6.6.6 Port F Registers (PTFD, PTFPE, PTFSE, and PTFDD) ..................................................92 6.6.7 Port G Registers (PTGD, PTGPE, PTGSE, and PTGDD) ..............................................93 Freescale Semiconductor Title Chapter 6 Parallel Input/Output MC9S08GB/GT Data Sheet, Rev. 2.3 Page 9 ...

  • Page 10

    ... ICG Control Register 2 (ICGC2) ......................................................................119 ICG Status Register 1 (ICGS1) .................................................................................120 7.5.3 7.5.4 ICG Status Register 2 (ICGS2) ........................................................................122 7.5.5 ICG Filter Registers (ICGFLTU, ICGFLTL) .......................................................122 ICG Trim Register (ICGTRM) ...........................................................................123 7.5.6 10 Title Chapter 7 MC9S08GB/GT Data Sheet, Rev. 2.3 Page Freescale Semiconductor ...

  • Page 11

    ... KBI Interrupt Controls ...................................................................................................148 9.5 KBI Registers and Control Bits .....................................................................................................148 9.5.1 KBI Status and Control Register (KBI1SC) ..................................................................148 9.5.2 KBI Pin Enable Register (KBI1PE) ..............................................................................150 Freescale Semiconductor Title Chapter 8 Central Processor Unit (CPU) Chapter 9 MC9S08GB/GT Data Sheet, Rev. 2.3 Page ...

  • Page 12

    ... Receiver Block Diagram ................................................................................................172 11.6.2 Data Sampling Technique ..............................................................................................174 11.6.3 Receiver Wakeup Operation ..........................................................................................174 11.6.3.1 Idle-Line Wakeup ..........................................................................................175 11.6.3.2 Address-Mark Wakeup .................................................................................175 11.7 Interrupts and Status Flags ............................................................................................................175 12 Title Chapter 10 Timer/PWM (TPM) Module Chapter 11 MC9S08GB/GT Data Sheet, Rev. 2.3 Page Freescale Semiconductor ...

  • Page 13

    ... SPI Control Register 1 (SPI1C1) ...................................................................................197 12.4.2 SPI Control Register 2 (SPI1C2) ...................................................................................198 12.4.3 SPI Baud Rate Register (SPI1BR) .................................................................................199 12.4.4 SPI Status Register (SPI1S) ...........................................................................................201 12.4.5 SPI Data Register (SPI1D) ............................................................................................202 Freescale Semiconductor Title Chapter 12 MC9S08GB/GT Data Sheet, Rev. 2.3 Page ...

  • Page 14

    ... Modes of Operation .......................................................................................................221 14.1.2.1 Stop Mode .....................................................................................................221 14.1.2.2 Power Down Mode .......................................................................................221 14.1.3 Block Diagram ...............................................................................................................221 14.2 Signal Description .........................................................................................................................222 14.2.1 Overview ........................................................................................................................222 14.2.1.1 Channel Input Pins — AD1P7–AD1P0 ........................................................223 14 Title Chapter 13 Chapter 14 MC9S08GB/GT Data Sheet, Rev. 2.3 Page Freescale Semiconductor ...

  • Page 15

    ... DBG Registers and Control Bits ....................................................................................252 15.5.3.1 Debug Comparator A High Register (DBGCAH) ........................................252 15.5.3.2 Debug Comparator A Low Register (DBGCAL) .........................................252 15.5.3.3 Debug Comparator B High Register (DBGCBH) .........................................252 15.5.3.4 Debug Comparator B Low Register (DBGCBL) ..........................................252 Freescale Semiconductor Title , V ........................................................223 REFH REFL , V ...

  • Page 16

    ... B.2 Mechanical Drawings ....................................................................................................................281 B.3 64-Pin LQFP Package Drawing ....................................................................................................282 B.4 48-Pin QFN Package Drawing ......................................................................................................283 B.5 44-Pin QFP Package Drawing .......................................................................................................284 B.6 42-Pin SDIP Package Drawing .....................................................................................................285 16 Title Appendix A Electrical Characteristics Appendix B MC9S08GB/GT Data Sheet, Rev. 2.3 Page Freescale Semiconductor ...

  • Page 17

    ... On-chip random-access memory (RAM) (see • 8-channel, 10-bit analog-to-digital converter (ATD) • Two serial communications interface modules (SCI) • Serial peripheral interface module (SPI) Freescale Semiconductor Chapter 15, “Development Table 1-1 for device specific information) MC9S08GB/GT Data Sheet, Rev. 2.3 Support”) 17 ...

  • Page 18

    ... Two 2-channel, 16-bit timers 2K Two 2-channel, 16-bit timers 1K Two 2-channel, 16-bit timers MC9S08GB/GT Data Sheet, Rev. 2.3 I/O Packages 56 64 LQFP 56 64 LQFP QFN 36 44 QFP 34 42 SDIP ( QFN 36 44 QFP 34 42 SDIP ( QFN 36 44 QFP 34 42 SDIP Freescale Semiconductor ...

  • Page 19

    ... IRQ does not have a clamp diode to V above Pin contains integrated pullup device. 5. High current drive 6. Pins PTA[7:4] contain both pullup and pulldown devices. Pulldown available when KBI enabled (KBIPn = 1). Freescale Semiconductor INTERNAL BUS DEBUG MODULE (DBG) 8-BIT KEYBOARD INTERRUPT MODULE (KBI1) IIC MODULE (IIC1) SERIAL COMMUNICATIONS ...

  • Page 20

    ... MC9S08GB/GT Data Sheet, Rev. 2.3 8 PTA7/KBI1P7– PTA0/KBI1P0 NOTES PTB7/AD1P7– NOTE 1 PTB0/AD1P0 PTC6 (NOTE 6) PTC5 (NOTE 6) PTC4 NOTES 1, 5 PTC3/SCL1 PTC2/SDA1 PTC1/RxD2 PTC0/TxD2 PTD4/TPM2CH1 PTD3/TPM2CH0 NOTE 1 PTD1/TPM1CH1 PTD0/TPM1CH0 PTE5/SPSCK1 PTE4/MOSI1 PTE3/MISO1 NOTE 1 PTE2/SS1 PTE1/RxD1 PTE0/TxD1 PTG2/EXTAL NOTE 1 PTG1/XTAL PTG0/BKGD/ Freescale Semiconductor ...

  • Page 21

    ... The external crystal oscillator — An external clock source — The output of the digitally-controlled oscillator (DCO) in the frequency-locked loop sub-module Control bits inside the ICG determine which source is connected. Freescale Semiconductor Table 1-2. Block Versions Module Analog-to-Digital Converter (ATD) Internal Clock Generator (ICG) ...

  • Page 22

    ... ICGLCLK — Development tools can select this internal self-clocked source (~ 8 MHz) to speed up BDC communications in systems where the bus clock is slow. • ICGERCLK — External reference clock can be selected as the real-time interrupt clock source. 22 MC9S08GB/GT Data Sheet, Rev. 2.3 Freescale Semiconductor ...

  • Page 23

    ... Device Pin Assignment 64 63 RESET 1 PTG7 2 PTC0/TxD2 3 PTC1/RxD2 4 PTC2/SDA1 5 PTC3/SCL1 6 PTC4 7 PTC5 8 PTC6 9 PTC7 10 PTF2 11 PTF3 12 PTF4 13 14 PTE0/TxD1 PTE1/RxD1 15 IRQ Figure 2-1. MC9S08GBxx in 64-Pin LQFP Package Freescale Semiconductor MC9S08GB/GT Data Sheet, Rev. 2 PTA2/KBI1P2 47 PTA1/KBI1P1 46 PTA0/KBI1P0 45 PTF7 44 PTF6 43 PTF5 42 V REFL ...

  • Page 24

    ... Chapter 2 Pins and Connections RESET 1 PTC0/TxD2 2 PTC1/RxD2 3 PTC2/SDA1 4 PTC3/SCL1 5 PTC4 6 PTC5 7 PTC6 8 PTC7 9 PTE0/TxD1 10 11 PTE1/RxD1 IRQ 12 Figure 2-2. MC9S08GTxx in 48-Pin QFN Package 24 MC9S08GB/GT Data Sheet, Rev. 2.3 PTA1/KBI1P1 36 PTA0/KBI1P0 REFL V 33 REFH PTB7/AD1P7 32 PTB6/AD1P6 31 PTB5/AD1P5 30 PTB4/AD1P4 29 PTB3/AD1P3 28 PTB2/AD1P2 27 PTB1/AD1P1 26 PTB0/AD1P0 25 Freescale Semiconductor ...

  • Page 25

    ... RESET 1 PTC0/TxD2 PTC1/RxD2 PTC2/SDA1 PTC3/SCL1 PTC4 PTC5 PTC6 PTE0/TxD1 PTE1/RxD1 IRQ 11 Figure 2-3. MC9S08GTxx in 44-Pin QFP Package Freescale Semiconductor MC9S08GB/GT Data Sheet, Rev. 2.3 Device Pin Assignment PTA1/KBI1P1 33 PTA0/KBI1P0 REFL V 30 REFH PTB7/AD1P7 29 PTB6/AD1P6 28 PTB5/AD1P5 27 PTB4/AD1P4 26 PTB3/AD1P3 25 PTB2/AD1P2 24 PTB1/AD1P1 23 25 ...

  • Page 26

    ... V 1 DDAD V 2 SSAD RESET PTC4 IRQ MC9S08GB/GT Data Sheet, Rev. 2.3 PTA7/KBI1P7 42 PTA6/KBI1P6 41 PTA5/KBI1P5 40 PTA4/KBI1P4 39 PTA3/KBI1P3 38 PTA2/KBI1P2 37 PTA1/KBI1P1 36 35 PTA0/KBI1P0 V 34 REFL 33 V REFH PTB7/AD1P7 32 PTB6/AD1P6 31 PTB5/AD1P5 30 PTB4/AD1P4 29 PTB3/AD1P3 28 PTB2/AD1P2 27 PTB1/AD1P1 26 PTB0/AD1P0 25 PTD4/TPM2CH1 24 PTD3/TPM2CH0 23 PTD1/TPM1CH1 22 Freescale Semiconductor ...

  • Page 27

    ... These are the PTG6 same pins as PTG7 PTG1 and PTG2. 3. BKGD/MS is the same pin as PTG0. 4. The 48-pin QFN has 2 V pins SS (V and V ), SS1 SS2 both of which must be connected to GND. Freescale Semiconductor V REFH V DDAD MC9S08GBxx C BYAD 0.1 µF V SSAD V REFL 0.1 µ ...

  • Page 28

    ... Internal power-on reset and low-voltage reset circuitry typically make external reset circuitry unnecessary. This pin is normally connected to the standard 6-pin background 28 Chapter 7, “Internal Clock Generator (ICG) (when used) and R S MC9S08GB/GT Data Sheet, Rev. 2.3 ) that is Self_reset Module.” should be low-inductance F Freescale Semiconductor ...

  • Page 29

    ... Immediately after reset, all 55 of these pins are configured as high-impedance general-purpose inputs with internal pullup devices disabled. Freescale Semiconductor , released, and sampled again approximately 38 Self_reset MC9S08GB/GT Data Sheet, Rev ...

  • Page 30

    ... Chapter 11, “Serial Communications Interface (SCI) Module” Chapter 6, “Parallel Input/Output” Chapter 6, “Parallel Input/Output” Chapter 7, “Internal Clock Generator (ICG) Module” Chapter 15, “Development Support” Chapter 6, “Parallel MC9S08GB/GT Data Sheet, Rev. 2.3 Chapter 6, “Parallel 1 Reference Input/Output” for details. Freescale Semiconductor ...

  • Page 31

    ... I/O N PTB6/AD1P6 I/O N PTB7/AD1P7 I/O N PTC0/TxD2 I/O Y PTC1/RxD2 I/O Y PTC2/SDA1 I/O Y PTC3/SCL1 I/O Y Freescale Semiconductor Table 2-2. Signal Properties Output 2 Pull-Up 1 Slew — — The 48-pin QFN package has two V — — and V SS2 — — — — — — — ...

  • Page 32

    ... Not available on 42-, or 44-pin pkg SWC SWC Not available on 42-, 44-, or 48-pin pkg SWC SWC Not available on 42-, 44-, or 48-pin pkg SWC SWC Not available on 42-, 44-, or 48-pin pkg SWC SWC Not available on 42-, 44-, or 48-pin pkg MC9S08GB/GT Data Sheet, Rev. 2.3 Comments Freescale Semiconductor ...

  • Page 33

    ... When encountering a BDC breakpoint • When encountering a DBG breakpoint After entering active background mode, the CPU is held in a suspended state waiting for serial background commands rather than executing instructions from the user’s application program. Freescale Semiconductor MC9S08GB/GT Data Sheet, Rev. 2.3 33 ...

  • Page 34

    ... MCU is operated in run mode for the first time. When the MC9S08GB/GT is shipped from the Freescale Semiconductor factory, the FLASH program memory is erased by default unless specifically noted so there is no program that could be executed in run mode until the FLASH memory is initially programmed ...

  • Page 35

    ... RAM. The voltage regulator low-power standby state the ATD. Upon entry into stop2, the states of the I/O pins are latched. The states are held while in stop2 mode and after exiting stop2 mode until written to PPDACK in SPMSC2. Freescale Semiconductor Table 3-1. Stop Mode Behavior RAM ...

  • Page 36

    ... CPU executes a STOP instruction, the system clocks to the background debug logic remain active when the MCU enters stop mode so background debug communication is still possible. In addition, 36 Chapter 15, “Development Support,” section of this data sheet. If ENBDM MC9S08GB/GT Data Sheet, Rev. 2.3 Freescale Semiconductor ...

  • Page 37

    ... When the MCU enters any stop mode, system clocks to the internal peripheral modules are stopped. Even in the exception case (ENBDM = 1), where clocks to the background debug logic continue to operate, clocks to the peripheral systems are halted to reduce power consumption. Refer to Mode,” Section 3.6.2, “Stop2 Mode,” and behavior in stop modes. Freescale Semiconductor RAM ICG ATD 1 Standby Active ...

  • Page 38

    ... If the MCU is configured to go into stop2 or stop1 mode, the IIC module will be reset upon wake-up from stop and must be reinitialized. Voltage Regulator — The voltage regulator enters a low-power standby state when the MCU enters any of the stop modes unless the LVD is enabled in stop mode or BDM is enabled. 38 MC9S08GB/GT Data Sheet, Rev. 2 conversion Freescale Semiconductor ...

  • Page 39

    ... Reset and Interrupt Vector Assignments Table 4-1 shows address assignments for reset and interrupt vectors. The vector names shown in this table are the labels used in the Freescale-provided equate file for the MC9S08GB/GT. For more details about Freescale Semiconductor $0000 DIRECT PAGE REGISTERS $007F ...

  • Page 40

    ... Low Voltage Detect IRQ SWI Reset MC9S08GB/GT Data Sheet, Rev. 2.3 Chapter 5, “Resets, Vector Name Vrti Viic1 Vatd1 Vkeyboard1 Vsci2tx Vsci2rx Vsci2err Vsci1tx Vsci1rx Vsci1err Vspi1 Vtpm2ovf Vtpm2ch4 Vtpm2ch3 Vtpm2ch2 Vtpm2ch1 Vtpm2ch0 Vtpm1ovf Vtpm1ch2 Vtpm1ch1 Vtpm1ch0 Vicg Vlvd Virq Vswi Vreset Freescale Semiconductor ...

  • Page 41

    ... Cells that are not associated with named bits are shaded. A shaded cell with a 0 indicates this unused bit always reads Shaded cells with dashes indicate unused or reserved bit locations that could read 0s. Freescale Semiconductor can use the more efficient direct addressing mode which only and Table 4-4 the whole address in column one is shown in bold ...

  • Page 42

    ... SBR11 SBR10 SBR9 SBR8 SBR3 SBR2 SBR1 SBR0 WAKE ILT RWU ORIE NEIE FEIE SBR11 SBR10 SBR9 SBR8 SBR3 SBR2 SBR1 SBR0 WAKE ILT RWU ORIE NEIE FEIE Freescale Semiconductor Bit 0 — PT SBK PF RAF PEIE Bit 0 PT SBK PF RAF PEIE Bit 0 ...

  • Page 43

    ... PTGDD7 $0048 ICGC1 0 $0049 ICGC2 LOLRE $004A ICGS1 $004B ICGS2 0 $004C ICGFLTU 0 $004D ICGFLTL $004E ICGTRM * This bit is reserved for Freescale Semiconductor internal use only. Always write this bit. Freescale Semiconductor SPE SPTIE MSTR 0 0 MODFEN SPPR2 SPPR1 SPPR0 0 SPTEF MODF 0 0 ...

  • Page 44

    ... ELS3B ELS3A ELS4B ELS4A — — — — — — Freescale Semiconductor Bit 0 0 Bit 0 Bit 0 — — RXAK — — PS0 Bit 8 Bit 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 0 Bit 8 Bit 0 — ...

  • Page 45

    ... During reset events, the contents of NVPROT and NVOPT in the nonvolatile register area of the FLASH memory are transferred into corresponding FPROT and FOPT working registers in the high-page registers to control security and block protection options. Freescale Semiconductor 4-3, are accessed much less often than other I/O and control registers Table 4-3. High-Page Register Summary ...

  • Page 46

    ... FPS1 — — — FNORED 0 0 ;point one past RAM ;SP<-(H:X-1) MC9S08GB/GT Data Sheet, Rev. 2 — — — — — — FPS0 0 0 — — — SEC01 Section 4.5, “Security” for a detailed Freescale Semiconductor Bit 0 — — 0 — SEC00 ...

  • Page 47

    ... FLASH erase and programming operations, in-application programming is also possible through other software-controlled communication paths. For a more detailed discussion of in-circuit and in-application programming, refer to the HCS08 Family Reference Manual, Volume I, Freescale Semiconductor document order number HCS08RMv1/D. 4.4.1 Features Features of the FLASH memory include: • ...

  • Page 48

    ... The command sequence must be completed by clearing FCBEF to launch the command. burst programming. The FCDIV register must be initialized before using any FLASH commands. This must be done only once following a reset. 48 NOTE Figure 4 flowchart for executing all of the commands except for MC9S08GB/GT Data Sheet, Rev. 2.3 Freescale Semiconductor ...

  • Page 49

    ... A5 through A0. A new row begins when addresses A5 through A0 are all zero. The first byte of a series of sequential bytes being programmed in burst mode will take the same amount of time to program as a byte programmed in standard mode. Subsequent bytes will program in the burst Freescale Semiconductor START 0 ...

  • Page 50

    ... WRITE COMMAND TO FCMD WRITE 1 TO FCBEF (2) Wait at least four bus cycles before TO LAUNCH COMMAND checking FCBEF or FCCF. (2) AND CLEAR FCBEF YES FPVIO OR FACCERR ? NO NEW BURST COMMAND ? NO 0 FCCF ? 1 DONE MC9S08GB/GT Data Sheet, Rev. 2.3 Only required once ERROR EXIT Freescale Semiconductor ...

  • Page 51

    ... One use for block protection is to block protect an area of FLASH memory for a bootloader program. This bootloader program then can be used to erase the rest of the FLASH memory and reprogram it. Because the bootloader is protected, it remains intact even if MCU power is lost in the middle of an erase and reprogram operation. Freescale Semiconductor MC9S08GB/GT Data Sheet, Rev. 2.3 FLASH NVPROT)”). ...

  • Page 52

    ... BKGD/MS low at the rising edge of reset. A user can choose to allow or disallow a security unlocking mechanism through an 8-byte backdoor security key. If the nonvolatile KEYEN bit in NVOPT/FOPT is 0, the backdoor key is disabled and there 52 MC9S08GB/GT Data Sheet, Rev. 2.3 Freescale Semiconductor ...

  • Page 53

    ... FLASH registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file normally is used to translate these names into the appropriate absolute addresses. Freescale Semiconductor MC9S08GB/GT Data Sheet, Rev. 2.3 FLASH Registers and Control Bits ...

  • Page 54

    ... PRDIV8 and DIV5:DIV0 for selected bus frequencies PRDIV8 DIV5 DIV4 DIV3 Unimplemented or Reserved ÷ ([DIV5:DIV0 FCLK Bus ÷ (8 × ([DIV5:DIV0 FCLK Bus MC9S08GB/GT Data Sheet, Rev. 2 Bit 0 DIV2 DIV1 DIV0 Eqn. 4-1 Eqn. 4-2 Freescale Semiconductor ...

  • Page 55

    ... NVBACKKEY+7, in that order), security is temporarily disengaged until the next MCU reset backdoor key access allowed. FNORED — Vector Redirection Disable When this bit is 1, vector redirection is disabled Vector redirection disabled Vector redirection enabled. Freescale Semiconductor Table 4-6. FLASH Clock Divider Settings DIV5:DIV0 f FCLK (Decimal) 12 192 ...

  • Page 56

    ... Background debug commands can write to FPROT. 56 “Security.” Table 4-7. Security States SEC01:SEC00 Description 0:0 secure 0:1 secure 1:0 unsecured 1:1 secure KEYACC Unimplemented or Reserved Section 4.5, “Security.” MC9S08GB/GT Data Sheet, Rev. 2.3 Table 4-7. When the MCU Bit Freescale Semiconductor ...

  • Page 57

    ... No redirection if FPOPEN = 0, or FNORED = 1. 2 Reset vector is not redirected. 3 32K and 60K devices only. 4 60K devices only. Freescale Semiconductor FPDIS FPS2 FPS1 (1) (1) (1) This register is loaded from nonvolatile location NVPROT during reset. = Unimplemented or Reserved Table 4-8) ...

  • Page 58

    ... FACCERR is cleared by writing FACCERR. Writing FACCERR has no meaning or effect access error has occurred access error has occurred FCCF FPVIOL FACCERR Unimplemented or Reserved Figure 4-8. FLASH Status Register (FSTAT) MC9S08GB/GT Data Sheet, Rev. 2 Bit 0 0 FBLANK Section 4.4.5, “Access Errors.” Freescale Semiconductor ...

  • Page 59

    ... Mass erase (all FLASH) All other command codes are illegal and generate an access error not necessary to perform a blank check command after a mass erase operation. Only blank check is required as part of the security unlocking mechanism. Freescale Semiconductor Execution” for a detailed discussion of FLASH 6 ...

  • Page 60

    ... Chapter 4 Memory 60 MC9S08GB/GT Data Sheet, Rev. 2.3 Freescale Semiconductor ...

  • Page 61

    ... Low-voltage detect (LVD) • Computer operating properly (COP) timer • Illegal opcode detect • Background debug forced reset • The reset pin (RESET) • Clock generator loss of lock and loss of clock reset Freescale Semiconductor MC9S08GB/GT Data Sheet, Rev. 2.3 Table 5-1) 61 ...

  • Page 62

    ... The user program initializes the stack pointer and performs other system setup before clearing the I bit to allow the CPU to respond to interrupts. 62 selected. The reset pin is driven low for 34 Self_reset Section 5.8.4, “System Options Register MC9S08GB/GT Data Sheet, Rev. 2.3 (SOPT)” for Freescale Semiconductor ...

  • Page 63

    ... SP points at the next available location on the stack which is the address that is one less than the address where the CCR was saved. The PC value that is stacked is the address of the instruction in the main program that would have executed next if the interrupt had not occurred. Freescale Semiconductor NOTE MC9S08GB/GT Data Sheet, Rev. 2.3 ...

  • Page 64

    ... CONDITION CODE REGISTER ACCUMULATOR * INDEX REGISTER (LOW BYTE X) PROGRAM COUNTER HIGH PROGRAM COUNTER LOW TOWARD HIGHER ADDRESSES * High byte (H) of index register is not automatically stacked. Figure 5-1. Interrupt Stack Frame MC9S08GB/GT Data Sheet, Rev. 2.3 SP AFTER INTERRUPT STACKING SP BEFORE THE INTERRUPT Freescale Semiconductor ...

  • Page 65

    ... CCR the CPU will finish the current instruction, stack the PCL, PCH and CCR CPU registers, set the I bit, and then fetch the interrupt vector for the highest priority pending interrupt. Processing then continues in the interrupt service routine. Freescale Semiconductor NOTE MC9S08GB/GT Data Sheet, Rev. 2.3 Interrupts – ...

  • Page 66

    ... CH0IE TPM2 channel 0 TOIE TPM1 overflow CH2IE TPM1 channel 2 CH1IE TPM1 channel 1 CH0IE TPM1 channel 0 LOLRE/LOCRE ICG LVDIE Low-voltage detect IRQIE IRQ pin — Software interrupt COPE Watchdog timer LVDRE Low-voltage detect — External pin — Illegal opcode Freescale Semiconductor ...

  • Page 67

    ... In run and wait modes, only the external clock can be used as the RTI's clock source. In stop2 mode, only the internal RTI clock can be used. In stop3, either the external clock or internal RTI clock can be used. Freescale Semiconductor level. Both the POR bit and the LVD bit in SRS are set ...

  • Page 68

    ... IRQ is rising edge or rising edge/high-level sensitive IRQ is falling edge or falling edge/low-level sensitive. 68 Chapter 4, “Memory,” of this data sheet for the absolute IRQF IRQEDG IRQPE Unimplemented or Reserved MC9S08GB/GT Data Sheet, Rev. 2.3 (SRTISC),” for detailed 2 1 Bit 0 0 IRQIE IRQMOD IRQACK Freescale Semiconductor ...

  • Page 69

    ... Writing any value to this register address clears the COP watchdog timer without affecting the contents of this register. The reset state of these bits depends on what caused the MCU to reset. Freescale Semiconductor Reset, Interrupt, and System Control Registers and Control Bits Sensitivity” ...

  • Page 70

    ... Reset was caused by an ICG module reset Reset caused by ICG module Reset not caused by ICG module PIN COP ILOP Writing any value to SIMRS address clears COP watchdog timer (1) (1) Figure 5-3. System Reset Status (SRS) MC9S08GB/GT Data Sheet, Rev. 2 Bit 0 0 ICG LVD ( Freescale Semiconductor ...

  • Page 71

    ... Bit 7 Read: COPE Write: Reset: 1 Figure 5-5. System Options Register (SOPT) Freescale Semiconductor Reset, Interrupt, and System Control Registers and Control Bits ...

  • Page 72

    ... The high-order 4 bits of address $1806 are hard coded to reflect the current mask set revision number (0–F cycles of BUSCLK). 13 cycles of BUSCLK REV2 REV1 REV0 1 (1) (1) ( ID6 ID5 ID4 Unimplemented or Reserved MC9S08GB/GT Data Sheet, Rev. 2 Bit 0 ID11 ID10 ID9 ID8 ID3 ID2 ID1 ID0 Freescale Semiconductor ...

  • Page 73

    ... These read/write bits select the wakeup period for the RTI. The clock source for the real-time interrupt is its own clock source, which oscillates with a period of approximately 1/f other MCU clock sources. Using an external clock source, the delays will be crystal frequency divided by value in RTIS2:RTIS1:RTIS0. Freescale Semiconductor Reset, Interrupt, and System Control Registers and Control Bits 6 5 ...

  • Page 74

    ... LVDRE LVDACK Unimplemented or Reserved MC9S08GB/GT Data Sheet, Rev. 2.3 2 External Clock Source Period = t ext Disable periodic wakeup timer t x 256 ext t x 1024 2048 4096 8192 ext t x 16384 ext t x 32768 ex Table A Bit (1) (1) LVDSE LVDE Freescale Semiconductor for details. ...

  • Page 75

    ... Low voltage warning is present or was present Low voltage warning not present. LVWACK — Low-Voltage Warning Acknowledge The LVWACK bit indicates the low-voltage warning acknowledge. Writing LVWACK clears LVWF low voltage warning is not present. Freescale Semiconductor Reset, Interrupt, and System Control Registers and Control Bits ...

  • Page 76

    ... The write-once PPDC bit controls which power down mode, stop1 or stop2, is selected Stop2, partial power down, mode enabled if PDC set Stop1, full power down, mode enabled if PDC set LVD = V ). LVD LVDH = V ). LVD LVDL ). LVW = V ). LVW LVWH = V ). LVW LVWL MC9S08GB/GT Data Sheet, Rev. 2.3 Freescale Semiconductor ...

  • Page 77

    ... Freescale Semiconductor Chapter 2, “Pins and NOTE MC9S08GB/GT Data Sheet, Rev. 2.3 Connections,” ...

  • Page 78

    ... PTC5 PTC4 NOTES 1, 5 PTC3/SCL1 PTC2/SDA1 PTC1/RxD2 PTC0/TxD2 PTD7/TPM2CH4 PTD6/TPM2CH3 PTD5/TPM2CH2 PTD4/TPM2CH1 NOTE 1 PTD3/TPM2CH0 PTD2/TPM1CH2 PTD1/TPM1CH1 PTD0/TPM1CH0 PTE7 PTE6 PTE5/SPSCK1 PTE4/MOSI1 NOTE 1 PTE3/MISO1 PTE2/SS1 PTE1/RxD1 PTE0/TxD1 8 PTF7–PTF0 NOTES 1, 5 PTG7 PTG6 PTG5 PTG4 NOTE 1 PTG3 PTG2/EXTAL PTG1/XTAL PTG0/BKGD/ Freescale Semiconductor ...

  • Page 79

    ... KBI inputs will be forced to act as inputs. Port A pins are available as general-purpose I/O pins controlled by the port A data (PTAD), data direction (PTADD), pullup enable (PTAPE), and slew rate control (PTASE) registers. Refer to I/O Controls,” for more information about general-purpose I/O control. Freescale Semiconductor PTA6/ ...

  • Page 80

    ... MC9S08GB/GT Data Sheet, Rev. 2.3 Chapter 9, “Keyboard Interrupt 2 1 Bit 0 PTB2/ PTB1/ PTB0/ AD1P2 AD1P1 AD1P0 Section 6.4, “Parallel Module,” for more information 2 1 Bit 0 PTC2/ PTC1/ PTC0/ SDA1 RxD2 TxD2 Section 6.4, “Parallel Module,” Module,” Freescale Semiconductor ...

  • Page 81

    ... When the SPI module is enabled, PTE2 serves as the SPI module’s slave select pin (SS1), PTE3 serves as the master-in slave-out pin (MISO1), PTE4 serves as the master-out slave-in pin (MOSI1), and PTE5 serves as the SPI clock pin (SPSCK1). Refer to more information about using PTE5–PTE2 as SPI pins. Freescale Semiconductor ...

  • Page 82

    ... Configuration”, and Chapter 15, “Development Module” for more information about using these pins MC9S08GB/GT Data Sheet, Rev. 2 Bit 0 PTF2 PTF1 PTF0 Section 6.4, “Parallel 2 1 Bit 0 PTG2/ PTG1/ PTG0/ EXTAL XTAL BKGD/MS Section 6.4, “Parallel Operation”, Support” for Freescale Semiconductor ...

  • Page 83

    ... Not all peripheral modules’ outputs have slew rate control; refer to Chapter 2, “Pins and rate control. Freescale Semiconductor Connections” for more information about which pins have slew MC9S08GB/GT Data Sheet, Rev. 2.3 Parallel I/O Controls ...

  • Page 84

    ... If the KBI takes control of a port A pin, the corresponding PTASE bit is ignored since the pin functions as an input. As long as PTADD is 0, the PTAPE controls the pullup enable for the KBI function. Reads of PTAD will return the logic value of the corresponding pin, provided PTADD MC9S08GB/GT Data Sheet, Rev. 2.3 Freescale Semiconductor ...

  • Page 85

    ... When any of bits 7 through 4 of port A are enabled as KBI inputs and are configured to detect rising edges/high levels, the pullup enable bits enable pulldown rather than pullup devices Internal pullup device enabled Internal pullup device disabled. Freescale Semiconductor ...

  • Page 86

    ... Write: Reset PTBD6 PTBD5 PTBD4 PTBD3 PTBPE6 PTBPE5 PTBPE4 PTBPE3 PTBSE6 PTBSE5 PTBSE4 PTBSE3 PTBDD6 PTBDD5 PTBDD4 PTBDD3 Figure 6-10. Port B Registers MC9S08GB/GT Data Sheet, Rev. 2 Bit 0 PTBD2 PTBD1 PTBD0 PTBPE2 PTBPE1 PTBPE0 PTBSE2 PTBSE1 PTBSE0 PTBDD2 PTBDD1 PTBDD0 Freescale Semiconductor ...

  • Page 87

    ... PTCPE can be used, provided the corresponding PTCDD bit provide a pullup device on the IIC serial data pin, when in receive mode. Reads of PTCD will return the logic value of the corresponding pin, provided PTCDD is 0. Freescale Semiconductor MC9S08GB/GT Data Sheet, Rev. 2.3 Parallel I/O Registers and Control Bits ...

  • Page 88

    ... For port B pins that are configured as inputs, these bits are ignored Slew rate control enabled Slew rate control disabled PTCD6 PTCD5 PTCD4 PTCD3 PTCPE6 PTCPE5 PTCPE4 PTCPE3 PTCSE6 PTCSE5 PTCSE4 PTCSE3 Figure 6-11. Port C Registers MC9S08GB/GT Data Sheet, Rev. 2 Bit 0 PTCD2 PTCD1 PTCD0 PTCPE2 PTCPE1 PTCPE0 PTCSE2 PTCSE1 PTCSE0 Freescale Semiconductor ...

  • Page 89

    ... Bit 7 Read: PTDD7 Write: Reset: 0 PTDPE Read: PTDPE7 Write: Reset: 0 PTDSE Read: PTDSE7 Write: Reset: 0 PTDDD Read: PTDDD7 PTDDD6 PTDDD5 PTDDD4 PTDDD3 PTDDD2 PTDDD1 PTDDD0 Write: Reset: 0 Freescale Semiconductor PTDD6 PTDD5 PTDD4 PTDD3 PTDPE6 PTDPE5 PTDPE4 PTDPE3 PTDSE6 PTDSE5 PTDSE4 PTDSE3 ...

  • Page 90

    ... SPI operational mode. PTEPE can be used, provided the corresponding PTEDD bit provide a pullup device on the SPI serial input pins (MOSI1 or MISO1) and slave select pin (SS1) depending on the SPI operational mode. Reads of PTED will return the logic value of the corresponding pin, provided PTEDD MC9S08GB/GT Data Sheet, Rev. 2.3 Freescale Semiconductor ...

  • Page 91

    ... PTESEn — Slew Rate Control Enable for Port E Bit 0–7) For port E pins that are outputs, these read/write control bits determine whether the slew rate controlled outputs are enabled. For port E pins that are configured as inputs, these bits are ignored Slew rate control enabled Slew rate control disabled. Freescale Semiconductor ...

  • Page 92

    ... PTFD6 PTFD5 PTFD4 PTFD3 PTFPE6 PTFPE5 PTFPE4 PTFPE3 PTFSE6 PTFSE5 PTFSE4 PTFSE3 PTFDD6 PTFDD5 PTFDD4 PTFDD3 Figure 6-14. Port F Registers MC9S08GB/GT Data Sheet, Rev. 2 Bit 0 PTFD2 PTFD1 PTFD0 PTFPE2 PTFPE1 PTFPE0 PTFSE2 PTFSE1 PTFSE0 PTFDD2 PTFDD1 PTFDD0 Freescale Semiconductor ...

  • Page 93

    ... G pin, the corresponding PTGD, PTGDD, PTGSE, and PTGPE bits are ignored. Reads of PTGD will return the logic value of the corresponding pin, provided PTGDD is 0. Freescale Semiconductor MC9S08GB/GT Data Sheet, Rev. 2.3 Parallel I/O Registers and Control Bits ...

  • Page 94

    ... For port G pins that are configured as inputs, these bits are ignored Slew rate control enabled Slew rate control disabled PTGD6 PTGD5 PTGD4 PTGD3 PTGPE6 PTGPE5 PTGPE4 PTGPE3 PTGSE6 PTGSE5 PTGSE4 PTGSE3 Figure 6-15. Port G Registers MC9S08GB/GT Data Sheet, Rev. 2 Bit 0 PTGD2 PTGD1 PTGD0 PTGPE2 PTGPE1 PTGPE0 PTGSE2 PTGSE1 PTGSE0 Freescale Semiconductor ...

  • Page 95

    ... These read/write bits control the direction of port G pins and what is read for PTGD reads Output driver enabled for port G bit n and PTGD reads return the contents of PTGDn Input (output driver disabled) and reads return the pin value. Freescale Semiconductor MC9S08GB/GT Data Sheet, Rev. 2.3 Parallel I/O Registers and Control Bits ...

  • Page 96

    ... Chapter 6 Parallel Input/Output 96 MC9S08GB/GT Data Sheet, Rev. 2.3 Freescale Semiconductor ...

  • Page 97

    ... CPU * ICGLCLK is the alternate BDC clock source for the MC9S08GB/GT. Figure 7-1. System Clock Distribution Diagram Freescale Semiconductor recommends that FLASH location $FFBE be reserved to store a nonvolatile version of ICGTRM. This will allow debugger and programmer vendors to perform a manual trim operation and store the resultant ICGTRM value for users to access at a later time. ...

  • Page 98

    ... PTC5 PTC4 NOTES 1, 5 PTC3/SCL1 PTC2/SDA1 PTC1/RxD2 PTC0/TxD2 PTD7/TPM2CH4 PTD6/TPM2CH3 PTD5/TPM2CH2 PTD4/TPM2CH1 NOTE 1 PTD3/TPM2CH0 PTD2/TPM1CH2 PTD1/TPM1CH1 PTD0/TPM1CH0 PTE7 PTE6 PTE5/SPSCK1 PTE4/MOSI1 NOTE 1 PTE3/MISO1 PTE2/SS1 PTE1/RxD1 PTE0/TxD1 8 PTF7–PTF0 NOTES 1, 5 PTG7 PTG6 PTG5 PTG4 NOTE 1 PTG3 PTG2/EXTAL PTG1/XTAL PTG0/BKGD/MS Freescale Semiconductor ...

  • Page 99

    ... One is designed to be approximately 8 MHz and can be selected as a local clock for the background debug controller. The other internal reference clock source is typically 243 kHz and can be trimmed for finer accuracy via software when a precise timed event is input to the MCU. This provides a highly reliable, low-cost clock source. Freescale Semiconductor ICG ICGERCLK ICGDCLK ...

  • Page 100

    ... Post-FLL divider selects bus rate divisors (/1 through /128) • Separate self-clocked source for real-time interrupt • Trimmable internal clock source supports SCI communications without additional external components • Automatic FLL engagement after lock is acquired 100 Section 7.4, “Initialization/Application MC9S08GB/GT Data Sheet, Rev. 2.3 Freescale Semiconductor ...

  • Page 101

    ... External Signal Description 7.2.1 Overview Table 7-1 shows the user-accessible signals available for the ICG. Name EXTAL XTAL Freescale Semiconductor Table 7-1. Signal Properties Function External clock/oscillator input Oscillator output MC9S08GB/GT Data Sheet, Rev. 2.3 External Signal Description Reset State Analog input ...

  • Page 102

    ... If an external crystal/resonator frequency reference is used, then the pins are connected as shown below. Recommended component values are listed in 102 ICG EXTAL V SS NOT CONNECTED Figure 7-4. External Clock Connections Appendix A, “Electrical MC9S08GB/GT Data Sheet, Rev. 2.3 XTAL Characteristics.” Freescale Semiconductor ...

  • Page 103

    ... When the oscillator is enabled in stop mode (OSCSTEN = 1), the individual clock generators are enabled but the clock feed to the rest of the MCU is turned off. This option is provided to avoid long oscillator startup times if necessary run the RTI from the oscillator during stop3. Freescale Semiconductor ICG EXTAL ...

  • Page 104

    ... FLL engaged (internal or external) as selected by the CLKS bits. 104 will default to f ICGDCLK Self_reset will maintain the previous frequency.If this mode ICGDCLK will be equal to the frequency of ICGDCLK before ICGDCLK MC9S08GB/GT Data Sheet, Rev. 2.3 which is nominally 8 MHz. If this Freescale Semiconductor ...

  • Page 105

    ... FLL Engaged Internal Unlocked FEI unlocked is a temporary state that is entered when FEI is entered and the count error (∆n) output from the subtractor is greater than the maximum n lock detector to detect the unlock condition. Freescale Semiconductor CLKS ICGIRCLK CLOCK SELECT CIRCUIT ...

  • Page 106

    ... Table 7 Because MHz is 40MHz, which is the , as required by the lock detector to detect the unlock MC9S08GB/GT Data Sheet, Rev. 2.3 or less than lock / R. ICGDCLK / external clock ICGERCLK Freescale Semiconductor ...

  • Page 107

    ... When the reference and/or DCO clock(s) are being monitored, if either one falls below a certain frequency, f LOR LOCS will remain set until it is cleared by software or until the MCU is reset. LOCS is cleared by reading Freescale Semiconductor / R. ICGDCLK for explanation of a comparison cycle) and passes this number to ...

  • Page 108

    ... Forced High 1 Real-Time X Real-Time Table 7-3 NOTE MC9S08GB/GT Data Sheet, Rev. 2.3 DCO Clock Clock Monitored? Monitored (1) No Yes (2) No Yes (2) No Yes (2) Yes Yes (2) Yes Yes No Yes Yes Yes No No Yes No Yes Yes shows the relationship between CLKS, Freescale Semiconductor ...

  • Page 109

    ... N) ÷ R ≥ 4 where P is determined by RANGE (see • MFD and RFD, respectively (see • LOCK = 1. If the above conditions are not true, then XCLK is equal to BUSCLK. Freescale Semiconductor Table 7-3. ICG State Table Reference Comparison Frequency Cycle Time ) ...

  • Page 110

    ... Bus used. Lowest power Highest clock accuracy Medium/High system cost (Crystal, resonator or external clock source required) IRG is off. DCO is off. NOTE MC9S08GB/GT Data Sheet, Rev. 2.3 Clock Reference Source = External < 20 MHz Bus range <= 8 MHz when crystal or resonator is Freescale Semiconductor ...

  • Page 111

    ... Register Bit 7 ICGC1 0 RANGE ICGC2 LOLRE ICGS1 CLKST ICGS2 0 ICGFLTU 0 ICGFLTL ICGTRM = Unimplemented or Reserved 1. This bit is reserved for Freescale Semiconductor internal use only. Any write operations to this register should write this bit. Freescale Semiconductor (1) f ICGOUT ICGDCLK ext (f / 7)* 64 IRG Range = 0 ...

  • Page 112

    ... Configures oscillator for low-frequency range; FLL prescale factor is 64 Oscillator using crystal or resonator is requested FLL engaged, external reference clock mode Oscillator disabled in stop modes Reserved for Freescale Semiconductor internal use; always write zero Unimplemented or reserved, always reads zero Generates an interrupt request on loss of lock Generates an interrupt request on loss of clock MC9S08GB/GT Data Sheet, Rev ...

  • Page 113

    ... Configures oscillator for high-frequency range; FLL prescale factor is 1 Requests an oscillator FLL engaged, external reference clock mode Disables the oscillator in stop modes Reserved for Freescale Semiconductor internal use; always write zero Unimplemented or reserved, always reads zero MC9S08GB/GT Data Sheet, Rev. 2.3 Initialization/Application Information ...

  • Page 114

    ... MHz on ICGOUT which corresponds MHz bus frequency (f 114 Generates an interrupt request on loss of lock Generates an interrupt request on loss of clock RECOVERY FROM STOP3 SERVICE INTERRUPT ICG1 = $7A ICG2 = $30 SOURCE (f CHECK NO CHECK LOCK = 1? FLL LOCK STATUS LOCK = 1? YES CONTINUE CONTINUE MC9S08GB/GT Data Sheet, Rev. 2 MHz) Bus NO YES ). Bus Freescale Semiconductor ...

  • Page 115

    ... Oscillator using crystal or resonator requested (don’t care) FLL engaged, internal reference clock mode Disables the oscillator in stop modes Reserved for Freescale Semiconductor internal use; always write zero Unimplemented or reserved, always reads zero Generates an interrupt request on loss of lock Generates an interrupt request on loss of clock Only need to write when trimming internal oscillator ...

  • Page 116

    ... Many other possible trimming procedures are valid and can be used. 116 RECOVERY FROM STOP3 CHECK FLL LOCK STATUS. LOCK = 1? NO CONTINUE NOTE: THIS WILL REQUIRE THE INTERAL REFERENCE CLOCK TO START AND STABILIZE. MC9S08GB/GT Data Sheet, Rev. 2.3 NO YES Freescale Semiconductor ...

  • Page 117

    ... Refer to the direct-page register summary in the assignments for all ICG registers. This section refers to registers and control bits only by their names. A Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. Freescale Semiconductor START TRIM PROCEDURE ICGTRM = $80 MEASURE ...

  • Page 118

    ... Write: Reset This bit is reserved for Freescale Semiconductor internal use only. Any write operations to this register should write this bit. RANGE — Frequency Range Select The RANGE bit controls the oscillator, reference divider, and FLL loop prescaler multiplication factor (P). It selects one of two reference frequency ranges for the ICG. The RANGE bit is write-once after a reset ...

  • Page 119

    ... MFD bits establishes the multiplication factor (N) applied to the reference frequency. Writes to the MFD bits will not take effect if a previous write is not complete. Select a low enough value for N such that f does not exceed its maximum specified value. ICGDCLK Freescale Semiconductor MFD ...

  • Page 120

    ... RFD Division Factor (R) ÷1 000 ÷2 001 ÷4 010 ÷8 011 ÷16 100 ÷32 101 ÷64 110 ÷128 111 CLKST REFST LOLS Unimplemented or Reserved Figure 7-15. ICG Status Register 1 (ICGS1) MC9S08GB/GT Data Sheet, Rev. 2 Bit 0 LOCK LOCS ERCS ICGIF Freescale Semiconductor ...

  • Page 121

    ... The ERCS bit is an indication of whether or not the external reference clock (ICGERCLK) meets the minimum frequency requirement External reference clock is stable, frequency requirement is met External reference clock is not stable, frequency requirement is not met. Freescale Semiconductor Table 7-9. CLKST Clock Mode Status Clock Status 00 ...

  • Page 122

    ... Reset: 0 Figure 7-17. ICG Upper Filter Register (ICGFLTU) 122 Unimplemented or Reserved Figure 7-16. ICG Status Register 2 (ICGS2) for two consecutive samples and the DCO clock is not static. This bit Unimplemented or Reserved MC9S08GB/GT Data Sheet, Rev. 2 Bit DCOS Bit 8 FLT Freescale Semiconductor ...

  • Page 123

    ... The TRIM bits control the internal reference generator frequency. They allow a ± 25% adjustment of the nominal (POR) period. The bit’s effect on period is binary weighted (i.e., bit 1 will adjust twice as much as changing bit 0). Increasing the binary value in TRIM will increase the period and decreasing the value will decrease the period. Freescale Semiconductor ...

  • Page 124

    ... Internal Clock Generator (ICG) Module 124 MC9S08GB/GT Data Sheet, Rev. 2.3 Freescale Semiconductor ...

  • Page 125

    ... This section provides summary information about the registers, addressing modes, and instruction set of the CPU of the HCS08 Family. For a more detailed discussion, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMv1/D. The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU. Several instructions and enhanced addressing modes were added to improve C compiler effi ...

  • Page 126

    ... Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions • STOP and WAIT instructions to invoke low-power operating modes 8.3 Programmer’s Model and CPU Registers Figure 8-1 shows the five CPU registers. CPU registers are not part of the memory map. 126 MC9S08GB/GT Data Sheet, Rev. 2.3 Freescale Semiconductor ...

  • Page 127

    ... X can be cleared, incremented, decremented, complemented, negated, shifted, or rotated. Transfer instructions allow data to be transferred from A or transferred to A where arithmetic and logical operations can then be performed. For compatibility with the earlier M68HC05 Family forced to $00 during reset. Reset has no effect on the contents of X. Freescale Semiconductor 7 0 ACCUMULATOR A ...

  • Page 128

    ... CCR bits, refer to the HCS08 Family Reference Manual, volume 1, Freescale Semiconductor document order number HCS08RMv1/D. CONDITION CODE REGISTER 128 CCR CARRY ZERO NEGATIVE INTERRUPT MASK HALF-CARRY (FROM BIT 3) TWO’S COMPLEMENT OVERFLOW Figure 8-2. Condition Code Register MC9S08GB/GT Data Sheet, Rev. 2.3 Freescale Semiconductor ...

  • Page 129

    ... Some instructions — such as bit test and branch, shift, and rotate — also clear or set the carry/borrow flag Carry out of bit carry out of bit 7 Freescale Semiconductor MC9S08GB/GT Data Sheet, Rev. 2.3 Programmer’s Model and CPU Registers 129 ...

  • Page 130

    ... This is faster and more memory efficient than specifying a complete 16-bit address for the operand. 130 MC9S08GB/GT Data Sheet, Rev. 2.3 Freescale Semiconductor ...

  • Page 131

    ... SP-Relative, 8-Bit Offset (SP1) This variation of indexed addressing uses the 16-bit value in the stack pointer (SP) plus an unsigned 8-bit offset included in the instruction as the address of the operand needed to complete the instruction. Freescale Semiconductor MC9S08GB/GT Data Sheet, Rev. 2.3 Addressing Modes 131 ...

  • Page 132

    ... After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent other interrupts while in the interrupt service routine. Although it is possible to clear the I bit with an instruction in the 132 Resets, Interrupts, and System Configuration MC9S08GB/GT Data Sheet, Rev. 2.3 Freescale Semiconductor ...

  • Page 133

    ... MCU even stop mode. Recovery from stop mode depends on the particular HCS08 and whether the oscillator was stopped in stop mode. Refer to the Modes of Operation Freescale Semiconductor chapter for more details. MC9S08GB/GT Data Sheet, Rev. 2.3 Special Operations ...

  • Page 134

    ... A 16-bit value in two consecutive memory locations. The higher-order (most significant) 8 bits are located at the address of M, and the lower-order (least significant) 8 bits are located at the next higher sequential address. 134 MC9S08GB/GT Data Sheet, Rev. 2.3 Table 8-1. Freescale Semiconductor ...

  • Page 135

    ... Any label or expression that evaluates to an unsigned 8-bit value, used for indexed addressing oprx16 — Any label or expression that evaluates to a 16-bit value. Because the HCS08 has a 16-bit address bus, this can be either a signed or an unsigned value. Freescale Semiconductor MC9S08GB/GT Data Sheet, Rev. 2.3 HCS08 Instruction Set Summary 135 ...

  • Page 136

    ... IMM A9 ii DIR B9 dd EXT IX2 – IX1 SP2 9ED9 ee ff SP1 9EE9 ff IMM AB ii DIR BB dd EXT IX2 – IX1 SP2 9EDB ee ff SP1 9EEB IMM A4 ii DIR B4 dd EXT IX2 – IX1 SP2 9ED4 ee ff SP1 9EE4 ff Freescale Semiconductor ...

  • Page 137

    ... Equal To (Signed Operands) Branch if Lower BLO rel (Same as BCS) BLS rel Branch if Lower or Same Branch if Less Than BLT rel (Signed Operands) Branch if Interrupt Mask BMC rel Clear Freescale Semiconductor Description Branch if ( – – – – – – REL Mn ← 0 – – – – – – ...

  • Page 138

    ... DIR (b6 DIR (b7 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 DIR IMM IMM IX1 IX SP1 9E61 DIR 3F dd INH 4F INH 5F INH 8C IX1 SP1 9E6F ff IMM A1 ii DIR B1 dd EXT IX2 – – IX1 SP2 9ED1 ee ff SP1 9EE1 ff Freescale Semiconductor ...

  • Page 139

    ... Jump JMP oprx8,X JMP ,X JSR opr8a JSR opr16a JSR oprx16,X Jump to Subroutine JSR oprx8,X JSR ,X Freescale Semiconductor Description ← (M)= $FF – (M) A ← (A) = $FF – (A) X ← (X) = $FF – (X) 0 – – M ← (M) = $FF – (M) M ← (M) = $FF – (M) M ← (M) = $FF – (M) (H:X) – ...

  • Page 140

    ... IX 78 SP1 9E68 ff DIR 34 dd INH 44 INH 54 – – 0 IX1 SP1 9E64 ff DIR/DIR DIR/IX – IMM/DIR IX+/DIR DIR 30 dd INH 40 INH 50 – – IX1 SP1 9E60 IMM AA ii DIR BA dd EXT IX2 – IX1 SP2 9EDA ee ff SP1 9EEA Freescale Semiconductor ...

  • Page 141

    ... STX oprx16,X Store X (Low 8 Bits of STX oprx8,X Index Register) STX ,X in Memory STX oprx16,SP STX oprx8,SP Freescale Semiconductor Description ← (SP + $0001); Pull (A) – – – – – – INH SP ← (SP + $0001); Pull (H) – – – – – – INH SP ← (SP + $0001); Pull (X) – ...

  • Page 142

    ... I bit ← 0; Halt CPU – – 0 – – – INH MC9S08GB/GT Data Sheet, Rev. 2.3 Effect on CCR IMM A0 ii DIR B0 dd EXT IX2 – – IX1 SP2 9ED0 ee ff SP1 9EE0 ff 83 INH DIR 3D dd INH 4D INH 5D – IX1 SP1 9E6D Freescale Semiconductor ...

  • Page 143

    ... IMM Immediate IX Indexed, No Offset DIR Direct IX1 Indexed, 8-Bit Offset EXT Extended IX2 Indexed, 16-Bit Offset DD DIR to DIR IMD IMM to DIR IX+D IX+ to DIR DIX+ DIR to IX+ Freescale Semiconductor Table 8-2. Opcode Map (Sheet Read-Modify-Write Control NEGX NEG NEG RTI 1 INH ...

  • Page 144

    ... IX 4 IX2 3 IX1 4 SP2 3 9EDF 5 9EEF STX 4 SP2 3 Prebyte (9E) and Opcode in 9E60 6 HCS08 Cycles Hexadecimal NEG Instruction Mnemonic Addressing Mode Number of Bytes 3 SP1 Freescale Semiconductor 4 SUB SP1 4 CMP SP1 4 SBC SP1 4 9EF3 6 CPX CPHX SP1 3 SP1 4 AND SP1 4 BIT SP1 4 LDA ...

  • Page 145

    ... Keyboard interrupts selectable on eight port pins: — Four falling-edge/low-level sensitive — Four falling-edge/low-level or rising-edge/high-level sensitive — Choice of edge-only or edge-and-level sensitivity — Common interrupt flag and interrupt enable control — Capable of waking up the MCU from stop3 or wait mode Freescale Semiconductor PTA6/ PTA5/ PTA4/ PTA3/ KBI1P6 ...

  • Page 146

    ... PTC5 PTC4 NOTES 1, 5 PTC3/SCL1 PTC2/SDA1 PTC1/RxD2 PTC0/TxD2 PTD7/TPM2CH4 PTD6/TPM2CH3 PTD5/TPM2CH2 PTD4/TPM2CH1 NOTE 1 PTD3/TPM2CH0 PTD2/TPM1CH2 PTD1/TPM1CH1 PTD0/TPM1CH0 PTE7 PTE6 PTE5/SPSCK1 PTE4/MOSI1 NOTE 1 PTE3/MISO1 PTE2/SS1 PTE1/RxD1 PTE0/TxD1 8 PTF7–PTF0 NOTES 1, 5 PTG7 PTG6 PTG5 PTG4 NOTE 1 PTG3 PTG2/EXTAL PTG1/XTAL PTG0/BKGD/ Freescale Semiconductor ...

  • Page 147

    ... Synchronous logic is used to detect edges. Prior to detecting an edge, enabled keyboard inputs in a KBI module must be at the deasserted logic level. A falling edge is detected when an enabled keyboard input signal is seen as a logic 1 (the deasserted level) during one bus cycle and then a logic 0 (the asserted level) during the next cycle. Freescale Semiconductor KBACK V RESET ...

  • Page 148

    ... KBI Status and Control Register (KBI1SC) Bit 7 Read: KBEDG7 KBEDG6 KBEDG5 KBEDG4 Write: Reset: 0 Figure 9-4. KBI Status and Control Register (KBI1SC) 148 Memory chapter of this data sheet for the absolute address KBF Unimplemented or Reserved MC9S08GB/GT Data Sheet, Rev. 2 Bit 0 0 KBIE KBIMOD KBACK Freescale Semiconductor ...

  • Page 149

    ... KBI port bits 7 through 4 can be configured to detect either: • Rising edges-only or rising edges and high levels (KBEDGn = 1) • Falling edges-only or falling edges and low levels (KBEDGn = Edge-and-level detection Edge-only detection. Freescale Semiconductor MC9S08GB/GT Data Sheet, Rev. 2.3 KBI Registers and Control Bits 149 ...

  • Page 150

    ... I/O pin Bit n of KBI port enabled as a keyboard interrupt input 0 = Bit n of KBI port is a general-purpose I/O pin not associated with the KBI. 150 KBIPE6 KBIPE5 KBIPE4 MC9S08GB/GT Data Sheet, Rev. 2 Bit 0 KBIPE3 KBIPE2 KBIPE1 KBIPE0 Freescale Semiconductor ...

  • Page 151

    ... Timer system enable • One interrupt per channel plus terminal count interrupt Freescale Semiconductor Section 7.3.9, “Fixed Frequency MC9S08GB/GT Data Sheet, Rev. 2.3 Clock”). Selecting XCLK as the 151 ...

  • Page 152

    ... PTC5 PTC4 NOTES 1, 5 PTC3/SCL1 PTC2/SDA1 PTC1/RxD2 PTC0/TxD2 PTD7/TPM2CH4 PTD6/TPM2CH3 PTD5/TPM2CH2 PTD4/TPM2CH1 NOTE 1 PTD3/TPM2CH0 PTD2/TPM1CH2 PTD1/TPM1CH1 PTD0/TPM1CH0 PTE7 PTE6 PTE5/SPSCK1 PTE4/MOSI1 NOTE 1 PTE3/MISO1 PTE2/SS1 PTE1/RxD1 PTE0/TxD1 8 PTF7–PTF0 NOTES 1, 5 PTG7 PTG6 PTG5 PTG4 NOTE 1 PTG3 PTG2/EXTAL PTG1/XTAL PTG0/BKGD/ Freescale Semiconductor ...

  • Page 153

    ... TPMxCnVH:TPMxCnVL 16-BIT LATCH The central component of the TPM is the 16-bit counter that can operate as a free-running counter, a modulo counter up-/down-counter when the TPM is configured for center-aligned PWM. The TPM Freescale Semiconductor Pins and Connections chapter for more information). CLOCK SOURCE ...

  • Page 154

    ... The TPM has center-aligned PWM capabilities controlled by the CPWMS control bit in TPMxSC. When CPWMS is set to 1, timer counter TPMxCNT changes to an up-/down-counter and all channels in the 154 Pins and Connections MC9S08GB/GT Data Sheet, Rev. 2.3 chapter for additional information Freescale Semiconductor ...

  • Page 155

    ... This corresponds to the end of a PWM period. (The $0000 count value corresponds to the center of a period.) Freescale Semiconductor Section 10.7.1, “Timer x Status and Control for more information about clock source selection. ...

  • Page 156

    ... TPM are configured for input capture or output compare functions. The period of this PWM signal is determined by the setting in the modulus register (TPMxMODH:TPMxMODL). The duty cycle is determined by the setting in the timer channel value 156 MC9S08GB/GT Data Sheet, Rev. 2.3 Freescale Semiconductor ...

  • Page 157

    ... If TPMxCnVH:TPMxCnVL is a positive value (bit 15 clear) and is greater than the (nonzero) modulus setting, the duty cycle will be 100 percent because the duty cycle compare will never occur. This implies the usable range of periods set by the modulus register is $0001 through $7FFE ($7FFF if Freescale Semiconductor OVERFLOW PERIOD ...

  • Page 158

    ... Writing to TPMxCnSC cancels any values written to the channel value registers and resets the coherency mechanism for TPMxCnVH:TPMxCnVL. 158 COUNT = 0 OUTPUT OUTPUT COMPARE COMPARE (COUNT UP) (COUNT DOWN) PULSE WIDTH 2 x PERIOD 2 x MC9S08GB/GT Data Sheet, Rev. 2.3 COUNT = TPMxMODH:TPMx Freescale Semiconductor ...

  • Page 159

    ... When a channel is configured as an output compare channel, the interrupt flag is set each time the main timer counter matches the 16-bit value in the channel value register. The flag is cleared by the 2-step sequence described in Section 10.6.1, “Clearing Timer Interrupt Freescale Semiconductor chapter for absolute interrupt vector addresses, priority, and local Flags.” Flags.” ...

  • Page 160

    ... Figure 10-5. Timer x Status and Control Register (TPMxSC) 160 Section 10.6.1, “Clearing Timer Interrupt Memory chapter of this data sheet for the absolute address TOIE CPWMS CLKSB CLKSA Unimplemented or Reserved MC9S08GB/GT Data Sheet, Rev. 2.3 Flags.” Bit 0 PS2 PS1 PS0 Freescale Semiconductor ...

  • Page 161

    ... When the TPMxCH0 pin is selected as the TPM clock source, the corresponding ELS0B:ELS0A control bits should be set to 0:0 so channel 0 does not try to use the same pin for a conflicting function. Freescale Semiconductor Table 10-1. TPM Clock Source Selection TPM Clock Source to Prescaler Input ...

  • Page 162

    ... Figure 10-7. Timer x Counter Register Low (TPMxCNTL) 162 Table 10-2. Prescale Divisor Selection TPM Clock Source Divided- Any write to TPMxCNTH clears the 16-bit counter Any write to TPMxCNTL clears the 16-bit counter MC9S08GB/GT Data Sheet, Rev. 2.3 Table 10-2. This 128 Bit Bit Bit Bit Freescale Semiconductor ...

  • Page 163

    ... Timer x Channel n Status and Control Register (TPMxCnSC) TPMxCnSC contains the channel interrupt status flag and control bits that are used to configure the interrupt enable, channel configuration, and pin function. Bit 7 Read: CHnF Write: Reset: 0 Figure 10-10. Timer x Channel n Status and Control Register (TPMxCnSC) Freescale Semiconductor ...

  • Page 164

    ... MSnA — Mode Select A for TPM Channel n When CPWMS = 0 and MSnB = 0, MSnA configures TPM channel n for input capture mode or output compare mode. Refer to Table 10-3 164 Table 10-3. for a summary of channel mode and setup controls. MC9S08GB/GT Data Sheet, Rev. 2.3 Freescale Semiconductor ...

  • Page 165

    ... These read/write registers contain the captured TPM counter value of the input capture function or the output compare value for the output compare or PWM functions. The channel value registers are cleared by reset. Freescale Semiconductor Mode Pin not used for TPM channel; use as an external clock for the TPM or ...

  • Page 166

    ... When both bytes have been written, they are transferred as a coherent 16-bit value into the timer channel value registers. This latching mechanism may be manually reset by writing to the TPMxCnSC register. This latching mechanism allows coherent 16-bit writes in either order, which is friendly to various compiler implementations. 166 MC9S08GB/GT Data Sheet, Rev. 2 Bit Bit Bit Bit Freescale Semiconductor ...

  • Page 167

    ... This SCI system offers many advanced features not commonly found on other asynchronous serial I/O peripherals on other embedded controllers. The receiver employs an advanced data sampling technique that ensures reliable communication and noise detection. Hardware parity, receiver wakeup, and double buffering on transmit and receive are also included. Freescale Semiconductor MC9S08GB/GT Data Sheet, Rev. 2.3 167 ...

  • Page 168

    ... PTC5 PTC4 NOTES 1, 5 PTC3/SCL1 PTC2/SDA1 PTC1/RxD2 PTC0/TxD2 PTD7/TPM2CH4 PTD6/TPM2CH3 PTD5/TPM2CH2 PTD4/TPM2CH1 NOTE 1 PTD3/TPM2CH0 PTD2/TPM1CH2 PTD1/TPM1CH1 PTD0/TPM1CH0 PTE7 PTE6 PTE5/SPSCK1 PTE4/MOSI1 NOTE 1 PTE3/MISO1 PTE2/SS1 PTE1/RxD1 PTE0/TxD1 8 PTF7–PTF0 NOTES 1, 5 PTG7 PTG6 PTG5 PTG4 NOTE 1 PTG3 PTG2/EXTAL PTG1/XTAL PTG0/BKGD/ Freescale Semiconductor ...

  • Page 169

    ... SCI communications require the transmitter and receiver (which typically derive baud rates from independent clock sources) to use the same baud rate. Allowed tolerance on this baud frequency depends on the details of how the receiver synchronizes to the leading edge of the start bit and how bit sampling is performed. Freescale Semiconductor MODULO DIVIDE BY (1 THROUGH 8191) DIVIDE BY ...

  • Page 170

    ... For a Freescale Semiconductor SCI system whose bus frequency is driven by a crystal, the allowed baud rate mismatch is about ±4.5 percent for 8-bit data format and about ± ...

  • Page 171

    ... SCIxD. Freescale Semiconductor (WRITE-ONLY) SCID – Tx BUFFER 11-BIT TRANSMIT SHIFT REGISTER ...

  • Page 172

    ... This action queues a break character to be sent as soon as the shifter is available. If SBK is still 1 when the queued break moves into the shifter (synchronized to the baud rate clock), an additional break character is queued. If the receiving device is another Freescale Semiconductor SCI, the break characters will be received all eight (or nine) data bits and a framing error (FE = 1). ...

  • Page 173

    ... The receiver is enabled by setting the RE bit in SCIxC2. Character frames consist of a start bit of logic 0, eight (or nine) data bits (LSB first), and a stop bit of logic 1. For information about 9-bit data mode, refer to Section 11.8.1, “8- and 9-Bit Data configured for normal 8-bit data mode. Freescale Semiconductor (READ-ONLY) SCID – Rx BUFFER DIVIDE BY 16 ...

  • Page 174

    ... SCI receiver. In such a system, all receivers evaluate the first character(s) of each message, and as soon as they determine the message is intended for a different receiver, they write logic 1 to the receiver wake up (RWU) control bit in SCIxC2. When RWU = 1, it 174 MC9S08GB/GT Data Sheet, Rev. 2.3 Section 11.7, Freescale Semiconductor ...

  • Page 175

    ... SCIxD. The RDRF flag is cleared by reading SCIxS1 while RDRF = 1 and then reading SCIxD. If the SCI is configured to operate in 9-bit mode, an additional read to the SCIxC3 register is required to clear RDRF Freescale Semiconductor MC9S08GB/GT Data Sheet, Rev. 2.3 Interrupts and Status Flags ...

  • Page 176

    ... During all stop modes, clocks to the SCI module are halted. In stop1 and stop2 modes, all SCI register data is lost and must be re-initialized upon recovery from these two stop modes. No SCI module registers are affected in stop3 mode. 176 MC9S08GB/GT Data Sheet, Rev. 2.3 Freescale Semiconductor ...

  • Page 177

    ... SCIxBDL. The working value in SCIxBDH does not change until SCIxBDL is written. SCIxBDL is reset to a non-zero value, so after reset the baud rate generator remains disabled until the first time the receiver or transmitter is enabled ( bits in SCIxC2 are written to 1). Freescale Semiconductor Memory section of this data sheet for the absolute address MC9S08GB/GT Data Sheet, Rev ...

  • Page 178

    ... RxD1 pin is not used by SCI Normal operation — RxD1 and TxD1 use separate pins. 178 SBR12 SBR11 Unimplemented or Reserved SBR6 SBR5 SBR4 SBR3 Unimplemented or Reserved SCISWAI RSRC M WAKE MC9S08GB/GT Data Sheet, Rev. 2 Bit 0 SBR10 SBR9 SBR8 Bit 0 SBR2 SBR1 SBR0 Bit 0 ILT Freescale Semiconductor ...

  • Page 179

    ... Even parity means the total number the data character, including the parity bit, is even Odd parity Even parity. Freescale Semiconductor Operation,” for more information. MC9S08GB/GT Data Sheet, Rev. 2.3 SCI Registers and Control Bits Section 11 ...

  • Page 180

    ... When TE is written to 0, the transmitter keeps control of the port TxD1 pin until any data, queued idle, or queued break character finishes transmitting before allowing the pin to revert to a general-purpose I/O pin. 180 TCIE RIE ILIE Idle,” MC9S08GB/GT Data Sheet, Rev. 2 Bit 0 RE RWU SBK for more details. Freescale Semiconductor ...

  • Page 181

    ... To clear TDRE, read SCIxS1 with TDRE = 1 and then write to the SCI data register (SCIxD Transmit data register (buffer) empty Transmit data register (buffer) full. Freescale Semiconductor Section 11.6.3, “Receiver Wakeup Section 11.5.2, “Send Break and 6 ...

  • Page 182

    ... RDRF has been set. IDLE will be set only once even if the receive line remains idle for an extended period Idle line was detected idle line detected. 182 MC9S08GB/GT Data Sheet, Rev. 2.3 Freescale Semiconductor ...

  • Page 183

    ... To clear PF, read SCIxS1 and then read the SCI data register (SCIxD Parity error parity error. 11.10.5 SCI x Status Register 2 (SCIxS2) This register has one read-only status flag. Writes have no effect. Bit 7 Read: 0 Write: Reset: 0 Figure 11-10. SCI x Status Register 2 (SCIxS2) Freescale Semiconductor Unimplemented or Reserved MC9S08GB/GT Data Sheet, Rev ...

  • Page 184

    ... TxD1 pin is an input in single-wire mode. ORIE — Overrun Interrupt Enable This bit enables the overrun flag (OR) to generate hardware interrupt requests Hardware interrupt requested when interrupts disabled (use polling). 184 TXDIR ORIE Unimplemented or Reserved MC9S08GB/GT Data Sheet, Rev. 2 Bit 0 NEIE FEIE PEIE Freescale Semiconductor ...

  • Page 185

    ... This register is actually two separate registers. Reads return the contents of the read-only receive data buffer and writes go to the write-only transmit data buffer. Reads and writes of this register are also involved in the automatic flag clearing mechanisms for the SCI status flags. Bit 7 Read: R7 Write: T7 Reset: 0 Freescale Semiconductor ...

  • Page 186

    ... Serial Communications Interface (SCI) Module 186 MC9S08GB/GT Data Sheet, Rev. 2.3 Freescale Semiconductor ...

  • Page 187

    ... SPI functionality are shared with port E pins 2–5. See the appendix for SPI electrical parametric information. When the SPI is enabled, the direction of pins is controlled by module configuration. If the SPI is disabled, all four pins can be used as general-purpose I/O. Freescale Semiconductor Appendix A, “Electrical MC9S08GB/GT Data Sheet, Rev. 2.3 Characteristics,” ...

  • Page 188

    ... PTC5 PTC4 NOTES 1, 5 PTC3/SCL1 PTC2/SDA1 PTC1/RxD2 PTC0/TxD2 PTD7/TPM2CH4 PTD6/TPM2CH3 PTD5/TPM2CH2 PTD4/TPM2CH1 NOTE 1 PTD3/TPM2CH0 PTD2/TPM1CH2 PTD1/TPM1CH1 PTD0/TPM1CH0 PTE7 PTE6 PTE5/SPSCK1 PTE4/MOSI1 NOTE 1 PTE3/MISO1 PTE2/SS1 PTE1/RxD1 PTE0/TxD1 8 PTF7–PTF0 NOTES 1, 5 PTG7 PTG6 PTG5 PTG4 NOTE 1 PTG3 PTG2/EXTAL PTG1/XTAL PTG0/BKGD/ Freescale Semiconductor ...

  • Page 189

    ... In this system, the master device has configured its SS1 pin as an optional slave select output. MASTER SPI SHIFTER CLOCK GENERATOR Freescale Semiconductor MOSI1 MOSI1 MISO1 MISO1 SPSCK1 SPSCK1 SS1 SS1 Figure 12-2. SPI System Connections MC9S08GB/GT Data Sheet, Rev. 2.3 SLAVE SPI SHIFTER 7 ...

  • Page 190

    ... MISO1, and the shifter input is routed from the MOSI1 pin. In the external SPI system, simply connect all SPSCK pins to each other, all MISO pins together, and all MOSI pins together. Peripheral devices often use slightly different names for these pins. 190 MC9S08GB/GT Data Sheet, Rev. 2.3 Freescale Semiconductor ...

  • Page 191

    ... ENABLE SPI SYSTEM SHIFT OUT SHIFT LSBFE DIRECTION BUS RATE SPIBR CLOCK CLOCK GENERATOR MASTER/SLAVE MSTR MODE SELECT Freescale Semiconductor Tx BUFFER (WRITE SPI1D) SHIFT SPI SHIFT REGISTER IN Rx BUFFER (READ SPI1D) SHIFT Rx BUFFER Tx BUFFER CLOCK FULL EMPTY CLOCK LOGIC MODE FAULT ...

  • Page 192

    ... PRESCALER CLOCK RATE DIVIDER DIVIDE 16, 32, 64, 128, or 256 SPPR2:SPPR1:SPPR0 SPR2:SPR1:SPR0 Figure 12-4. SPI Baud Rate Generation for more details. MC9S08GB/GT Data Sheet, Rev. 2.3 MASTER DIVIDE BY SPI BIT RATE Freescale Semiconductor ...

  • Page 193

    ... SPSCK (CPOL = 0) SPSCK (CPOL = 1) SAMPLE IN (MISO OR MOSI) MOSI (MASTER OUT) MSB FIRST LSB FIRST MISO (SLAVE OUT) SS OUT (MASTER (SLAVE) Freescale Semiconductor 1 2 ... BIT 7 BIT 6 ... BIT 0 BIT 1 ... Figure 12-5. SPI Clock Formats (CPHA = 1) MC9S08GB/GT Data Sheet, Rev. 2.3 Functional Description BIT 2 ...

  • Page 194

    ... SAMPLE IN (MISO OR MOSI) MOSI (MASTER OUT) MSB FIRST BIT 7 LSB FIRST BIT 0 MISO (SLAVE OUT) SS OUT (MASTER (SLAVE) 194 2 ... 6 BIT 6 ... BIT 2 BIT 1 BIT 5 ... Figure 12-6. SPI Clock Formats (CPHA = 0) MC9S08GB/GT Data Sheet, Rev. 2 BIT 1 BIT 0 BIT 6 BIT 7 Freescale Semiconductor ...

  • Page 195

    ... I/O pin. When the SPI is enabled as a master and MODFEN = 1, the slave select output enable bit determines whether this pin acts as the mode fault input (SSOE = the slave select output (SSOE = 1). Freescale Semiconductor MC9S08GB/GT Data Sheet, Rev. 2.3 Functional Description ...

  • Page 196

    ... SPI registers. This section refers to registers and control bits only by their names, and a Freescale-provided equate or header file is used to translate these names into the appropriate absolute addresses. 196 Memory chapter of this data sheet for the absolute address MC9S08GB/GT Data Sheet, Rev. 2.3 Freescale Semiconductor ...

  • Page 197

    ... This bit selects one of two clock formats for different kinds of synchronous serial peripheral devices. Refer to Section 12.3.1, “SPI Clock 1 = First edge on SPSCK occurs at the start of the first cycle of an 8-cycle data transfer First edge on SPSCK occurs at the middle of the first cycle of an 8-cycle data transfer. Freescale Semiconductor SPE ...

  • Page 198

    ... SS input for mode fault Automatic SS output MODFEN BIDIROE Unimplemented or Reserved MC9S08GB/GT Data Sheet, Rev. 2.3 Table 12-1. Slave Mode Slave select input Slave select input Slave select input Slave select input Bit 0 0 SPISWAI SPC0 Table 12-1 for more Freescale Semiconductor ...

  • Page 199

    ... SPPR2:SPPR1:SPPR0 — SPI Baud Rate Prescale Divisor This 3-bit field selects one of eight divisors for the SPI baud rate prescaler as shown in input to this prescaler is the bus rate clock (BUSCLK). The output of this prescaler drives the input of the SPI baud rate divider (see Freescale Semiconductor ...

  • Page 200

    ... Prescaler Divisor 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 Table 12-3. SPI Baud Rate Divisor Rate Divisor 0:0:0 0:0:1 0:1:0 0:1:1 1:0:0 1:0:1 1:1:0 1:1:1 MC9S08GB/GT Data Sheet, Rev. 2 Figure 12-3. The Figure 12-4). The output of this 128 256 Freescale Semiconductor ...