MC9S08GT60CFD Freescale Semiconductor, MC9S08GT60CFD Datasheet - Page 161

• Manufacturer Part Number: MC9S08GT60CFD
• Description: MCU 8BIT 60K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08GT60CFD

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

TOF — Timer Overflow Flag
TOIE — Timer Overflow Interrupt Enable
CPWMS — Center-Aligned PWM Select
CLKSB:CLKSA — Clock Source Select
Freescale Semiconductor
This flag is set when the TPM counter changes to $0000 after reaching the modulo value programmed
in the TPM counter modulo registers. When the TPM is configured for CPWM, TOF is set after the
counter has reached the value in the modulo register, at the transition to the next lower count value.
Clear TOF by reading the TPM status and control register when TOF is set and then writing a 0 to TOF.
If another TPM overflow occurs before the clearing sequence is complete, the sequence is reset so TOF
would remain set after the clear sequence was completed for the earlier TOF. Reset clears the TOF bit.
Writing a 1 to TOF has no effect.
This read/write bit enables TPM overflow interrupts. If TOIE is set, an interrupt is generated when
TOF equals 1. Reset clears TOIE.
This read/write bit selects CPWM operating mode. Reset clears this bit so the TPM operates in
up-counting mode for input capture, output compare, and edge-aligned PWM functions. Setting
CPWMS reconfigures the TPM to operate in up-/down-counting mode for CPWM functions. Reset
clears the CPWMS bit.
As shown in
sources to drive the counter prescaler. The external source and the XCLK are synchronized to the bus
clock by an on-chip synchronization circuit.
1 = TPM counter has overflowed.
0 = TPM counter has not reached modulo value or overflow.
1 = TOF interrupts enabled.
0 = TOF interrupts inhibited (use software polling).
1 = All TPMx channels operate in center-aligned PWM mode.
0 = All TPMx channels operate as input capture, output compare, or edge-aligned PWM mode as
selected by the MSnB:MSnA control bits in each channel’s status and control register.
1. The maximum frequency that is allowed as an external clock is one-fourth of the bus
2. When the TPMxCH0 pin is selected as the TPM clock source, the corresponding
frequency.
ELS0B:ELS0A control bits should be set to 0:0 so channel 0 does not try to use the same pin
for a conflicting function.
Table
CLKSB:CLKSA
10-1, this 2-bit field is used to disable the TPM system or select one of three clock
0:0
0:1
1:0
1:1
Table 10-1. TPM Clock Source Selection
No clock selected (TPM disabled)
Bus rate clock (BUSCLK)
Fixed system clock (XCLK)
External source (TPMx Ext Clk)
MC9S08GB/GT Data Sheet, Rev. 2.3
TPM Clock Source to Prescaler Input
1
,
2
TPM Registers and Control Bits
161