MC9S08GT60CFD Freescale Semiconductor, MC9S08GT60CFD Datasheet - Page 165

• Manufacturer Part Number: MC9S08GT60CFD
• Description: MCU 8BIT 60K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08GT60CFD

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

If the associated port pin is not stable for at least two bus clock cycles before changing to input capture
mode, it is possible to get an unexpected indication of an edge trigger. Typically, a program would clear
status flags after changing channel configuration bits and before enabling channel interrupts or using the
status flags to avoid any unexpected behavior.
ELSnB:ELSnA — Edge/Level Select Bits
10.7.5
These read/write registers contain the captured TPM counter value of the input capture function or the
output compare value for the output compare or PWM functions. The channel value registers are cleared
by reset.
Freescale Semiconductor
CPWMS
Depending on the operating mode for the timer channel as set by CPWMS:MSnB:MSnA and shown
in
the level that will be driven in response to an output compare match, or select the polarity of the PWM
output.
Setting ELSnB:ELSnA to 0:0 configures the related timer pin as a general-purpose I/O pin unrelated
to any timer channel functions. This function is typically used to temporarily disable an input capture
channel or to make the timer pin available as a general-purpose I/O pin when the associated timer
channel is set up as a software timer that does not require the use of a pin. This is also the setting
required for channel 0 when the TPMxCH0 pin is used as an external clock input.
X
0
1
Table
Timer x Channel Value Registers (TPMxCnVH:TPMxCnVL)
10-3, these bits select the polarity of the input edge that triggers an input capture event, select
MSnB:MSnA
XX
XX
1X
00
01
ELSnB:ELSnA
Table 10-3. Mode, Edge, and Level Selection
X1
X1
00
01
10
11
00
01
10
11
10
10
MC9S08GB/GT Data Sheet, Rev. 2.3
Pin not used for TPM channel; use as an external clock for the TPM or
revert to general-purpose I/O
Output compare
Center-aligned
Input capture
Edge-aligned
Mode
PWM
PWM
Capture on rising edge only
Capture on falling edge only
Capture on rising or falling edge
Software compare only
Toggle output on compare
Clear output on compare
Set output on compare
High-true pulses (clear output on compare)
Low-true pulses (set output on compare)
High-true pulses (clear output on compare-up)
Low-true pulses (set output on compare-up)
Configuration
TPM Registers and Control Bits
165