MC9S08GT60CFD Freescale Semiconductor, MC9S08GT60CFD Datasheet - Page 197

• Manufacturer Part Number: MC9S08GT60CFD
• Description: MCU 8BIT 60K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08GT60CFD

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.4.1
This read/write register includes the SPI enable control, interrupt enables, and configuration options.
SPIE — SPI Interrupt Enable (for SPRF and MODF)
SPE — SPI System Enable
SPTIE — SPI Transmit Interrupt Enable
MSTR — Master/Slave Mode Select
CPOL — Clock Polarity
CPHA — Clock Phase
Freescale Semiconductor
This is the interrupt enable for SPI receive buffer full (SPRF) and mode fault (MODF) events.
Disabling the SPI halts any transfer that is in progress, clears data buffers, and initializes internal state
machines. SPRF is cleared and SPTEF is set to indicate the SPI transmit data buffer is empty.
This is the interrupt enable bit for SPI transmit buffer empty (SPTEF).
This bit effectively places an inverter in series with the clock signal from a master SPI or to a slave SPI
device. Refer to
This bit selects one of two clock formats for different kinds of synchronous serial peripheral devices.
Refer to
1 = When SPRF or MODF is 1, request a hardware interrupt.
0 = Interrupts from SPRF and MODF inhibited (use polling).
1 = SPI system enabled.
0 = SPI system inactive.
1 = When SPTEF is 1, hardware interrupt requested.
0 = Interrupts from SPTEF inhibited (use polling).
1 = SPI module configured as a master SPI device.
0 = SPI module configured as a slave SPI device.
1 = Active-low SPI clock (idles high).
0 = Active-high SPI clock (idles low).
1 = First edge on SPSCK occurs at the start of the first cycle of an 8-cycle data transfer.
0 = First edge on SPSCK occurs at the middle of the first cycle of an 8-cycle data transfer.
SPI Control Register 1 (SPI1C1)
Section 12.3.1, “SPI Clock
Section 12.3.1, “SPI Clock
Reset:
Read:
Write:
SPIE
Bit 7
Figure 12-7. SPI Control Register 1 (SPI1C1)
0
MC9S08GB/GT Data Sheet, Rev. 2.3
SPE
Formats,” for more details.
6
0
SPTIE
Formats,”
5
0
MSTR
for more details.
4
0
CPOL
3
0
CPHA
2
1
SPI Registers and Control Bits
SSOE
1
0
LSBFE
Bit 0
0
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